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  • EEVblog #4 – Low Power Calculator Design and FPGAs

    Posted on April 16th, 2009 EEVblog 12 comments

    Dodgy low power calculator design, Annoying FPGA’s, LCD’s, & Mr Bean

    EEVblog #4 Podcast

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    • Curtisbeef

      Awesome videos :) keep them coming and ill keep watching them.

    • http://www.tablix.org/~avian/blog Toma

      Hi

      I like how you show that operating a calculator at higher CPU frequency means shorter battery life, even if you take into account that the calculation takes longer.

      However, you should really take more care with units when doing calculations like that. uW/s makes no sense at all and you have amps squared on one side of the equals sign and watts on the other.

      • http://www.alternatezone.com/eevblog admin

        We aren’t in school here, this is real back-of-the-envelope engineering :-P
        It helps to think in terms of uW per finite processing time in this app, so it makes perfect sense to have uW/time for this application, and is of course simple and appropriate for explanatory purposes.

        • Alex

          I don’t understand how you figured the power/second. I would have thought that the factor of ten would have produced the power consumption after 10 seconds.

          Sorry to rehash something so long after the initial posting.

          I’ve been watching your videos since I got home from work today – it’s 12:45 in the morning here in Arizona. Awesome stuff. Much appreciated.

    • Cyrille de Brebisson

      hello,

      Sorry I “ticked you off” with the power management of the 20b…

      I will try to make things better to only going to high speed when doing calculations that I know are likely to be slow in the future…

      cyrille

      • http://www.alternatezone.com/eevblog admin

        Thanks Cyrille, it looks like constructive criticism is appreciated at HP!

    • http://ryndin.ru JessicaMaW

      Great point and very interesting food for thought. I’m not sure I have any clients I can replicate this with, but will bear in mind for the future. Regards

    • John W.

      I use an HP50g, which is the graphing/scientific calculator based around an ARM CPU, normally running at 75MHz, up to something like 200MHz changeable in software. The thing DEVOURS batteries, even using NiMH AAA’s. However, given the feature set and being an RPN calculator (which I have fallen in love with, I have a lot of trouble going back to my ancient Ti83+ with algebraic entry), I can deal with the battery life. Plus, the calculator can talk to my HP LaserJet5 (once I get the Infrared receiver dongle thing…), so I’m holding out to see how that works.

    • http://none sak

      Congrats for the blog, I’m quite a fan.

      Now keep up he rad with the FPGAs pin count. I’d really love to see
      a high density FPGA in a small count DIP package. That would be
      awesome. But no. Our friends from Xilinx and Altera,
      or even the smaller guys, don’t think it worths the effort.

      Now if I’m not mistaking this was all the same with micros until
      Microchip and Atmel decided to innovate with powerful small
      DIP packages, integrated ISP flash, etc. and started selling like crazy.

      When is this coming to FPGAs?

      Keep up the good work.

    • http://www.overmapped.com/ Jakob Eriksson

      Yes. In the meantime, couldn’t someone create a DIP PCB with an FPGA on it? Would be awesome.

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    • http://to.ly/tuLF Kulkarni

      Hello! I’ve been reading your blog for a long time now and finally got the bravery to go ahead and give you a
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