10 responses to “EEVblog #260 – Tracking Pre-Regulator Simulation in LTspice – PSU Part 13”

• Jorge Garcia March 22nd, 2012 at 04:18

  Hi Dave,

  Very nice I like these types of videos. It was very cool to include the footage of the snag you hit in LTSpice it’s a common problem in most simulators since Semiconductors are generally difficult to model properly due to the non-linear equations that model their behavior.

  I would recommend that you have a ferrite bead LC filter between the output of the switcher and the input of the linear regulator. Linear regulators are designed to suppress ripple at rectified AC frequencies and below( <= 120Hz), the switching transitions generate speaks with high frequency harmonic content which just bypasses the linear regulator's input and straight the output.

  By putting in a good filter you can avoid this high frequency noise making it to the output of your linear regulator. Check out this video by the late Jim Williams for more info.

  http://www.youtube.com/watch?v=WxhjLIu-vPg

  Keep up the good work.

  Jorge Garcia
  Cadsoft Support

  Reply

  • Jay Ts March 22nd, 2012 at 13:12

    Jorge wrote:
    > Semiconductors are generally difficult to model …

    Right, and this is especially true for various kinds of field-effect transistors. The equations used to model them are theoretical, and even at best, are inaccurate. But there are even bigger problems.

    Even for a given model of device, different manufacturers use different manufacturing processes, resulting in different values of, and relationships between, threshold voltages, drain currents, and transconductances. A simple way to think of it is a straight line on an x-y graph: the x-intercept is near the threshold voltage, and there is a slope to the linear part of the FET’s transfer characteristic. Even if the threshold voltage is the same, the drain current varies from device to device, and more between devices made by different manufacturers. Along with that, manufacturers may target different “typical” values whether one is specified on the datasheet or not, while still only guaranteeing a a very wide range of tolerable values.

    Even within production batch, there is variation in threshold voltage and Idss, and if you test many samples, you will probably find that there is a more-or-less linear relationship between the two. But in a different batch, or from a different manufacturer, you may see a different offset or slope of that line.

    Also, things change depending on the temperature of the die while the device is at its bias point in the circuit, if it is biased to be “on”.

    The result of all this is that there is no way a single Spice model can be used to accurately simulate a FET model for all circuits. (MOSFETs are not nearly as difficult as jFETs, which is mostly what I have studied, but the same basic ideas apply.)

    So Dave, before committing to your new design and having PC boards manufactured, I suggest you get some real FETs and the other parts you need, and try breadboarding. If you want to use Spice for something, you can create a Spice model for the FET (specific manufacturer and model) you choose, and then vary the threshold voltage in the Spice model to make sure your circuit works with all possible devices. Spice is good for that because even if you buy 1000 actual devices, you will probably just be getting devices in one batch, and will not see all possible variations from that manufacturer.

    Sorry I wrote so much. Actually, it was difficult to keep it this short! Cheers.

    Reply

• Worf March 22nd, 2012 at 09:40

  Here comes rev D of the schematic.

  Any bets on what the revision will be on the first production version?

  Reply

  • Bill Clay March 23rd, 2012 at 05:09

    There may never be, you heard Dave, he loves to “tinker” with the design. ;-/

    Reply

• JPL March 23rd, 2012 at 12:34

  I think I’d much rather use a PNP. Threshold voltages are nowhere near as predictable (unit to unit or lot to lot) as the base-emitter voltage.

  Reply

  • MPS April 29th, 2012 at 03:09

    Indeed a PNP gives much better control. If you add an emitter resistor you have great way to adjust the voltage difference accurately.

    Reply

• Drone March 23rd, 2012 at 23:21

  Dave,

  When you video LTSpice plots, turn on “Tools > Waveforms > Plot with thick lines”. Then we might actually be able to see the traces.

  I agree with JPL, use a transistor instead of a FET, more perdictable and much better temperature characteristics; both are important for production level units.

  I like your use of the LED. Many would drop a Zener in there, which again raises the spectre of temperature variation.

  Keep an eye on how the noise and spurious of the switching pre-regulator compromises your linear regulator’s output. If I were you I would find a way to keep the heat sink and maintain a very low-noise non-switching design. These days with ever lower supply voltages and lower current drain, it’s often all about supply noise.

  Regards, David in Jakarta

  Reply

• Steve March 29th, 2012 at 02:06

  OnSemi have a small circuit to generate a fixed amount of boost for a boost SMPS. It uses a circuit that isn’t reliant on such a fickle parameter as Vgs(th).

  Not sure if it can be employed here, but maybe worth a look.

  https://www.onsemi.com/pub_link/Collateral/DN06022-D.PDF

  Reply

• Piotr March 31st, 2012 at 00:56

  This is a very interesing post, thanks!

  Reply

• Marc G. April 30th, 2012 at 06:40

  Dave,

  I don’t think the simulation problem has anything to do with the feedback loop around the LT3080. I think the problem has to do with the use of a boost regulator. When power is applied, the input voltage goes right through the inductor and catch diode charging up the output cap. But since the LT3080 has zero output at this time, the FET is allowing this voltage to be driven to the feedback pin immediately, driving it above the setpoint. The boost converter then never switches and you’re stuck at this incorrect voltage.

  HTH,
  Marc

  Reply