4 - Layer PCB Power Plane Help

[diyaudio]

Hi

I'm busy developing my first 4-layer board, I am confused about setting up a power plane, I have several core voltages 12v (input), 3.3v (LDO), 1.2v (LDO) and some areas have 5v (Switching Regulator) how do I go about setting up a power plane for these voltages? Do I split the pwr plane for these different voltages?

 
 

 

 

[T3sl4co1l]

Don't use a "power plane", that's a holdout from archaic tools, I'm pretty sure.  Altium still supports that type of design, but the options are very limited.

Configure the inner layers as "signal" and use polygon pours to connect the supply nets.  This gives you relative freedom in design (routing and shape), without having to do bizarre cutouts and stuff, and you get polygon design rules.

You almost always want the top inner layer to be solid GND.  Exceptions might include, slots to isolate noisy and sensitive sections (use with caution), or sections that are completely isolated.

The bottom inner layer can then be whichever supplies are best.  If signal quality is not a concern, you might not even bother with pours, and use it as a third routing layer instead (providing space for more signals, as well as routed power).

The most common approach is to use pours extending under the areas where each supply net is dominant.  So, under your... whatever is using 1.2V (FPGA? DSP?), you at least want that extending underneath, and over to whichever pins are connecting to it.  But immediately around that pour, you need 3.3V for the VCCIO connections (or whatever), so you need that wrapping around.  Over in the analog section, you might use 5 or 12V as the pour.

If the 5V is only an intermediate, not used for anything else, then it certainly doesn't need to be routed elsewhere on the board.  Keep it confined to the power supply section.  Or, if you have just a few uses of it, it can be routed on the top or bottom as a normal signal, where it won't disturb the inner layers.

If you do wind up putting traces on inner layers, mind the negative space around those traces.  Everywhere there's a trace, there's no pour, but rather a slot in it.  Slots resonate at high frequencies, and below resonance, appear as increased inductance.  These can be stitched over, just as you would do ground stitching on a two layer board, but the advantage of a 4-layer board is to avoid stitching in the first place, so try to avoid the need for that.

If your board is relatively low density, you can achieve even higher copper density, and therefore less ground loop voltage drop and better shielding, by pouring ground (or another convenient, well-bypassed supply) on the top and bottom layers, too.  These will need to be stitched to be effective.

Tim

[diyaudio]

Don't use a "power plane", that's a holdout from archaic tools, I'm pretty sure.  Altium still supports that type of design, but the options are very limited.

Configure the inner layers as "signal" and use polygon pours to connect the supply nets.  This gives you relative freedom in design (routing and shape), without having to do bizarre cutouts and stuff, and you get polygon design rules.

You almost always want the top inner layer to be solid GND.  Exceptions might include, slots to isolate noisy and sensitive sections (use with caution), or sections that are completely isolated.

The bottom inner layer can then be whichever supplies are best.  If signal quality is not a concern, you might not even bother with pours, and use it as a third routing layer instead (providing space for more signals, as well as routed power).

The most common approach is to use pours extending under the areas where each supply net is dominant.  So, under your... whatever is using 1.2V (FPGA? DSP?), you at least want that extending underneath, and over to whichever pins are connecting to it.  But immediately around that pour, you need 3.3V for the VCCIO connections (or whatever), so you need that wrapping around.  Over in the analog section, you might use 5 or 12V as the pour.

If the 5V is only an intermediate, not used for anything else, then it certainly doesn't need to be routed elsewhere on the board.  Keep it confined to the power supply section.  Or, if you have just a few uses of it, it can be routed on the top or bottom as a normal signal, where it won't disturb the inner layers.

If you do wind up putting traces on inner layers, mind the negative space around those traces.  Everywhere there's a trace, there's no pour, but rather a slot in it.  Slots resonate at high frequencies, and below resonance, appear as increased inductance.  These can be stitched over, just as you would do ground stitching on a two layer board, but the advantage of a 4-layer board is to avoid stitching in the first place, so try to avoid the need for that.

If your board is relatively low density, you can achieve even higher copper density, and therefore less ground loop voltage drop and better shielding, by pouring ground (or another convenient, well-bypassed supply) on the top and bottom layers, too.  These will need to be stitched to be effective.

Tim

Hi Tim.

Firstly thanks for the tips, very helpful,  I had a feeling that changing the power pour to a signal layer on the layer stack manager would be better. I did of course keep the internal ground though. (Layer 3)

The processor I'm working with is a Analog Devices SHARC ADSP-21261 DSP, its a 144-PIN LQFP, rated at 150MHz, with lots of core 1.2v (about 15 or so pins) and about 10 pins for the 3.3v 

I started this afternoon with the power supply it looks something like this. see attachment. I'm open any criticism. 
 
Thanks for the tips.
 

 

[Skimask]

If I may add another Q onto the original...
How about spacing?  As in the isolation between the ground/power pour and any other signals...
In the past, I've used .050" for isolation on the top and bottom layer...in case the need arises to go back and do some rework...far less chance of shorting to anything else.
On the internal planes, is it better/safer to go with a much tighter isolation, say .010", if anything, just to cover more area?  Is there a 'standard', say double the minimum trace width or something?

[DerekG]

How about spacing?  As in the isolation between the ground/power pour and any other signals...

If you are using higher voltages, then you should use the internationally published standards for your clearances as a minimum.

If you are using low voltages, then the main reason for not making your clearances to little (small) is to increase the reliability at manufacture. You obviously need to weigh this up against what you need to put on the board & how much real estate you have.

Everyone has their own preferences, however when manufacturing 1000s of production boards, we have found 18mil (0.018") tracks & clearances provide very reliable boards.

If your earth/power nets are pushing some current, you may have to make your tracks wider of course.

Many users will use 10mil tracks, however the reliability when manufacturing thousands of boards will be lower. Most faults will be picked up at manufacture during bare board testing, however the more boards that are rejected, the higher the cost to the board shop (which is likely to be passed on to you next time around).

We often leave 24mil clearances to ground planes, as any shorts can take a lot of time to locate.

Remember, others will scoff & say they have no trouble with boards using 6mil tracks & clearances. At the end of the day, it is all about how much you have to squeeze onto the board.

[guscrown]

18 mil traces even for signals? How do you attached a trace that big to say, a 0402 resistor? or an IC with small pins? bottle down to 10mil?

[DerekG]

18 mil traces even for signals? How do you attached a trace that big to say, a 0402 resistor? or an IC with small pins? bottle down to 10mil?

Very easy with Diptrace which automatically necks-down to the pad width. You don't even need to think about it.

[marshallh]

Use a system of polygon pours



As you can see I have cheated on this layer for some signals. Always better to slice up the power fill rather than creating ground slots.

I use 8/10mil clearance on internal layers. Some fabs may have looser specs on internal layers.

In altium you can ctrl-click on any net to highlight it. Very useful for confirming that you didn't slice up your polygons into a thin sliver of ineffectiveness.



These 2 designs really should have been 6/8 layer but they weren't. If you are a bit less demanding you can have much cleaner power layers.

[guscrown]

18 mil traces even for signals? How do you attached a trace that big to say, a 0402 resistor? or an IC with small pins? bottle down to 10mil?

Very easy with Diptrace which automatically necks-down to the pad width. You don't even need to think about it.

Oh, makes sense. I'm on Altium and as far as I know it doesn't do that. at least my configuration doesn't do that.

[c4757p]

18 mil traces even for signals? How do you attached a trace that big to say, a 0402 resistor? or an IC with small pins? bottle down to 10mil?

18 mil is 0.46 mm. I routinely route 0.6 mm traces directly to 0402 pads, which themselves are 0.6 mm in width.

0402 = 40 x 20 mil

[T3sl4co1l]

If you're going to do that, you should make sure the traces exit the ends of the pads, not the sides, or even diagonals really.  Asymmetrical pads on small parts make for tombstoning problems.

Tim