Author Topic: Any pointers for improving large design layout performance in AD18?  (Read 1356 times)

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Offline oyvkar

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I'm in the process of evaluating Altium and other EDA packages for working with quite large designs.

The design I am working on contains a repeated structure, and some support circuitry for the repeated stuff. The repeated block is repeated 100 times. This totals to about 10 000 components over a 30x30 cm (10 layers) board. In Altium (18.0.11) I'm creating the channels using the Repeat feature.

As a novice user I feel like I am stepping in numerous pitfalls, causing performance to drop. Right now I am noticing that some operations are particularly time-consuming, and others are somewhat laggy. Performing an ECO update takes around 5 minutes after changing/removing 1 of the 150 components in the repeated cell. When doing routing with the "interactively route connections" tool, the frames per second is low, and the system spends 2-10 seconds after finishing a connection doing some sort of "analyzing" operation. For reference the system is a Ryzen 1800X, 1050ti GPU and 32 GB RAM.

I found that turning off Online DRC and anti-aliasing gave large performance boosts. Are there any other settings that could have particularly large impact on performance?

I'm also interested to hear what are your best design practices for working with very large designs within Altium are.
 

Offline Philfreeze

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #1 on: February 04, 2018, 11:25:07 pm »
I have never worked with such a large design so I cannot really help you. However, I would contact Altium support, pretty sure they would happily help you out in your evaluation.
 
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Offline T3sl4co1l

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #2 on: February 04, 2018, 11:31:41 pm »
Is Show Clearance Boundaries (CTRL+W during trace routing) turned on?  That tends to go slow, too.

Avoid using polygons in such a large design; use inner planes.  (With 10 layers, I'm guessing you already are!)  Even one repeated polygon will take a hundred instances of repour.  Obviously, this is kind of bothersome if you have some power components in the circuit.  Workarounds with hand-crafted traces or Regions may be desirable.

It may be practical to lay out the channels on a separate board, one instance at a time, then copy and propagate the placement and routing.  Placement can be done by hand, or copied in spreadsheet form on the PCB List panel, or from file (Tools / Component Placement / Place From File).

Needless to say, on this scale, anything you can do to optimize the circuit itself will be very valuable, both in layout time, board area, and especially BOM and assembly cost!

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 
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Offline jayatIBM

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #3 on: February 09, 2018, 02:01:00 am »
I'd recommend using a high end tool like Allegro.  At the company I work for we see a lot of benefits
 

Offline oyvkar

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #4 on: February 10, 2018, 12:07:39 am »
Interesting..

We are evaluating Altium, Allegro and PADS Professional.

For now it seems like Allegro and PADS handle large designs much more gracefully, but Altiums "copy room formats" is stronger than the similar features in Allegro/PADS.
 

Offline HWgeek

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #5 on: February 15, 2018, 01:06:15 am »
Although I too haven't worked with quite that large a design, I have used the multichannel design elements.  We found that turning off polygon rebuilding, and/or removing polygons (pushing as much as possible into pwr/gnd planes)  helps a lot.

If you aren't doing PCIe Gen 4 type of designs Allegro will be over kill, as well as having a badly dated and non-intuitive interface. 
Yes Allegro has more tool integrations with their other tools (Sigrity etc.) than I think Altium has  currently.

Having used both, I much prefer Altium for its smoother work flow, windows compliant GUI (copy/paste zooming etc.) and presentation.
Allegro's constraint manager is a bad throwback nightmare on how not to do a contraints interface.
If and when Allegro actually updates their UI to be modern and use modern controls (their windows mode only half works, half the time) Altium is overall an easier product to learn and use.

Outside of doing some of the super high speed stuff (and Altium is catching up in that regard)  where I have to worry about propagation delays with via's and traces, and back drilling, and keeping things matched to 1 mil or less, its not worth going to Allegro.
 

Offline Bud

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #6 on: February 16, 2018, 04:17:44 pm »
Avoid using polygons in such a large design; use inner planes.  (With 10 layers, I'm guessing you already are!)  Even one repeated polygon will take a hundred instances of repour. 

Can't you shelf polygons to improve speed?
 

Offline T3sl4co1l

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Re: Any pointers for improving large design layout performance in AD18?
« Reply #7 on: February 16, 2018, 06:38:40 pm »
Avoid using polygons in such a large design; use inner planes.  (With 10 layers, I'm guessing you already are!)  Even one repeated polygon will take a hundred instances of repour. 

Can't you shelf polygons to improve speed?

Sure, but then you can't edit them; and they still need to be reproduced and repoured, at least once, in a multichannel design.  That could take minutes, tens of minutes perhaps, even with the improved pour algorithm since ~AD16.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 


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