Is Show Clearance Boundaries (CTRL+W during trace routing) turned on? That tends to go slow, too.
Avoid using polygons in such a large design; use inner planes. (With 10 layers, I'm guessing you already are!) Even one repeated polygon will take a hundred instances of repour. Obviously, this is kind of bothersome if you have some power components in the circuit. Workarounds with hand-crafted traces or Regions may be desirable.
It may be practical to lay out the channels on a separate board, one instance at a time, then copy and propagate the placement and routing. Placement can be done by hand, or copied in spreadsheet form on the PCB List panel, or from file (Tools / Component Placement / Place From File).
Needless to say, on this scale, anything you can do to optimize the circuit itself will be very valuable, both in layout time, board area, and especially BOM and assembly cost!
Tim