Electrical clearance controlling between layers

[Kanc1erz]

Hello there.
Is there any possibility to create such rule to control electrical clearance between layers as well? For instance there is an ATEX requirement to assure minimum 0.5mm clearance between two tracks or components' pads and within one layer it works, clearly, however when core between top-layer and midlayer-1 is e.g. 0.3mm there is no problem to route a track under a component or track on top layer, which, in this case, is forbidden. I wonder, whether there is a possibility rule above mentioned. If yes - where can I find it? Or how to build a proper query?
We have AD in ver. 18 and 9.

Thanks in advance for any suggestions :-)

[fourtytwo42]

I think you had better be specific what this requirement is and post a link to it, something makes me think you are either misreading it or misapplying it BUT if you are talking about IEC60950 insulation requirements for example then tracks of different circuits on different layers are NOT allowed in proximity PERIOD.

[Neilm]

This depends on the safety standard you are working to. I know that some standards allow what you are asking for but there are some restrictions. You need a couple of layers of pre-preg between them and each must be rated for the voltage you require. You will have to I have not seen any real way of defining that in any CAD package I have used, other than showing 2 layers of prepreg in the board stackup. Of coourse, if your voltages are either side of the FR4 core, there is no problem.

[T3sl4co1l]

I think you had better be specific what this requirement is and post a link to it, something makes me think you are either misreading it or misapplying it BUT if you are talking about IEC60950 insulation requirements for example then tracks of different circuits on different layers are NOT allowed in proximity PERIOD.

In proximity to what?

60950-1 is clear about insulation inside PCBs -- it is a solid cemented joint, giving quite favorable ratings indeed.

Tim

[T3sl4co1l]

Hello there.
Is there any possibility to create such rule to control electrical clearance between layers as well? For instance there is an ATEX requirement to assure minimum 0.5mm clearance between two tracks or components' pads and within one layer it works, clearly, however when core between top-layer and midlayer-1 is e.g. 0.3mm there is no problem to route a track under a component or track on top layer, which, in this case, is forbidden. I wonder, whether there is a possibility rule above mentioned. If yes - where can I find it? Or how to build a proper query?
We have AD in ver. 18 and 9.

Thanks in advance for any suggestions :-)

In AD, layers are only on the Layer Stack Manager, and not driven by anything else.  Layer properties are not used by anything else, except for impedance calculation (when planes are present), component placement (the "flipped on layer" setting), 3D height, and probably some things with flex / board regions things.

AFAIK, rules do not check between layers, so you cannot set e.g. a straight-line clearance from copper on layer 1 to copper on layer 2, taking layer thickness into account (which I don't think can be referenced as a variable anyway, you'd have to update it manually).  Like if you need a 0.5mm distance in a 0.2mm dielectric, you need a 0.3mm clearance between layers.

Completely separate from the CAD tools -- on a design review level alone -- I would be deeply concerned about any design that depends so critically upon the PCB fab following the drawing correctly!

Tim

[fourtytwo42]

I think you had better be specific what this requirement is and post a link to it, something makes me think you are either misreading it or misapplying it BUT if you are talking about IEC60950 insulation requirements for example then tracks of different circuits on different layers are NOT allowed in proximity PERIOD.

In proximity to what?

60950-1 is clear about insulation inside PCBs -- it is a solid cemented joint, giving quite favorable ratings indeed.

Tim

For example primary and secondary circuits requiring 4mm creepage and clearance, maybe I should have been more explicit.

[KrudyZ]

I think you had better be specific what this requirement is and post a link to it, something makes me think you are either misreading it or misapplying it BUT if you are talking about IEC60950 insulation requirements for example then tracks of different circuits on different layers are NOT allowed in proximity PERIOD.

In proximity to what?

60950-1 is clear about insulation inside PCBs -- it is a solid cemented joint, giving quite favorable ratings indeed.

Tim

For example primary and secondary circuits requiring 4mm creepage and clearance, maybe I should have been more explicit.

Creepage and clearance numbers do not apply if the conductors are surrounded by insulation with sufficient breakdown voltage.
Therefore layer to layer trace distances are based only on the breakdown voltage of the dielectric between the layers.
On a two layer board, this might be compromised by holes or proximity to the edge of a board as this could provide a creepage path resulting in a lower maximum voltage.
Traces on inner layers are very good indeed, since they normally have neither a clearance nor a clearance path unless there is delamination.

[fourtytwo42]

I dont think that can be right otherwise why would SMPS manufactures go to extreme lengths to ensure there is only clear pcb with no copper on any layer across the primary to secondary isolation barrier ? Are you saying we are all misguided ?

[T3sl4co1l]

Simple: they go to extreme lengths to build their products on single layer boards...

Tim

[fourtytwo42]

Simple: they go to extreme lengths to build their products on single layer boards...
Tim

Ahh I understand, I do apologise, let's just say I err on the side of extreme caution and ensure I can see right through the board! Just an old fuddy duddy, sorry OP for corrupting your thread.

[T3sl4co1l]

Now, I have seen a lot of boards that you can see straight through the board, and they did use multilayer.  So, there may be reasons, or there may just be paranoia.  You're not wrong for asking!

Personally, I've done a few boards with layers all over the place, which have passed UL508.  Keep creepage and clearance alright and you're fine with that (and, yeah, internal layer clearance doesn't need much).

And I've done multilayer boards with see-through gaps.  The inner layers don't need as much clearance as the outer layers, and the outer layers don't have to be in the same places -- they could be overlapping, for instance, so long as creepage is still met around whatever edges there are.  The biggest reason is probably just aesthetic.  It looks nice, having everything lined up.  It doesn't use any more copper than needed (on the inner layers).  Electrical reasons are low on the list, but can be relevant: you do want lots of clearance (even on inner layers) where capacitance is a limiting factor, say on an isolated gate driver.

Tim

[floobydust]

Oops! Pic is of a PCB edge, and underneath Phoenix Contact terminal block.

Spacings between top-bottom outside layers (at an edge or slot), clearance underneath components or between components - PCB CADD fails.

If Altium was a smart company, they would add a creepage/clearance engine instead of a zillion rules that pretty much guarantee a mistake.
But you still need to think really really hard, or just hi-pot test a prototype.

[ahbushnell]

Oops! Pic is of a PCB edge, and underneath Phoenix Contact terminal block.

Spacings between top-bottom outside layers (at an edge or slot), clearance underneath components or between components - PCB CADD fails.

If Altium was a smart company, they would add a creepage/clearance engine instead of a zillion rules that pretty much guarantee a mistake.
But you still need to think really really hard, or just hi-pot test a prototype.

Looks to me like poor design. 

[T3sl4co1l]

A comprehensive creepage/clearance engine would be cool, yes.  You'd need ways to input boundary conditions for 3D models, to demonstrate issues like what are pictured.  That would take a lot of work, and I don't think STEP files are very suitable for that (even when they come in proper colors rather than solid uncolored mesh..).

More work just means more opportunity to screw up, and more places to hide those screw-ups.  Consider the audit output of such a check: it might include the rule settings (so you can see if any quirky things have been special-cased), and the results of applying those rules.  What's likely not in that audit, are the data which went into the check: boundary conditions of the components, which conducting and insulating features resulted in those decisions, and what distances and paths those objects passed or failed on.  When the shit hits the fan and a cause (or scapegoat) must be found, all these data will be brought to light, sooner or later, and at much greater expense (e.g., discovery in a lawsuit) than checking it out in the first place.

The present "best practice" is to subject the design to an independent review, i.e., UL or other NRTL.  They are just as fallible as any other engineering firm, but they back that up with a guarantee: they take liability for design failures, not you.  It's expensive, but not much more so than hiring a consultant to check the work -- and that wouldn't carry a guarantee.

So the key there is: work.  If it can be done with less user input, more automation and greater reliability, it's a win.  Otherwise, it's not much better than how things are today.  Sucks, but that's how things go.

Tim

[floobydust]

Products are constantly pushed to be smaller, so it's getting harder and harder to ensure PCB creepage and clearances are safe.
3D CADD is not quite there yet to help, and in Altium it's primitive wading through PCB design rules. Then people get false confidence.

Why can't I highlight a connection at the schematic level as HV and define relationships to other nodes there, instead of figuring out what NETP4_1 and other net labels are so I make a clearance rule from the ground up, again, and again. Altium knows the stackup, so (solid insulation) spacings between layers could also be monitored.

My experience with UL/CSA, they don't take any liability for their errors.
They would not expose themselves to recalls, damages etc. You sign that in the contract.
The end result is being told "remove the approval sticker" and that's about it.

[ajb]

Why can't I highlight a connection at the schematic level as HV and define relationships to other nodes there, instead of figuring out what NETP4_1 and other net labels are so I make a clearance rule from the ground up, again, and again.

You can.  Use a directive object in the schematic to assign those nets to a net class, then use the net class to establish a rule in the PCB.  (You can also use directives to directly assign PCB design rules to nets from the schematic, but that seems more cumbersome.)  To deal with many nets at once, you can attach a directive to a blanket, then any pins, net labels, ports, or sheet entries covered by the blanket will be subject to the directive.  Blankets will cover members of harnesses and I assume buses as well, but again, only if the blanket covers an object that establishes connectivity, like a port, label, or connector.

Altium Documentation