So it's not really a matched net length, but a matched subnet length? Should you be using From-Tos? Or a clock distributor or buffer to minimize the mismatch at the source? (Yes, the buffer itself may have much worse delay matching than your PCB layout, making that a silly solution. On the other hand, if it has to be that precise, surely you're screwed regardless, and some means of fine adjustment will be necessary anyway?)
Anyway, there's an example in the Altium docs of using a net bridge to fan out symmetrical delays. That's another option.
Tim