No, overlay is only printed over soldermask. PCB manufacturers almost always cut silk over exposed copper pads.
I normally draw the 3D outline (usually as a body on Mech 13) based on the "typical" dimensions in the datasheet. Silk, I draw the same outline oversized by one grid space (0.1/0.2 mm, or 5/10 mil, as appropriate to the part), over what places it can be drawn -- a chip resistor gets only two parallel lines, truncated by the pads (or if the pads are very close together, a single line segment down the middle). I try to use a silk outline representative of the component outline (say, if it has bumps and knobs sticking out), and include some notable features (e.g., the inner profile of a connector, or polarizing marks). I use Mech 1 for the center coordinate (a small cross; I think Altium defaults this to Mech 15), and draw the courtyard rectangle (on Mech 15) one grid space oversized from any silk, 3D or copper feature (so, for devices with profiles smaller than their pads -- chip resistors, SOICs, etc., the edge of the line is touching the edge of the pads; or bounding the silk outline for components that span their footprints, e.g., radial TH electrolytics).
STEP models are preferred where available, otherwise, 3D primitives until it looks kinda-sorta correct (body, housing, pins, etc.). 3D data is added whenever possible. No extra marks on other layers, labels, etc. Only good looking things.
Speaking of labels, and other layers, on the PCB, I usually hide the name of non-populated test points, show comments of most wires and connectors, and for mechanical features (holes, fiducials), move the name to Drill Drawing so they are identified on the mechanical outline.
Tim