Author Topic: How do I remove necks and dead copper on internal planes?  (Read 173 times)

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Offline dmg

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How do I remove necks and dead copper on internal planes?
« on: January 12, 2017, 03:43:21 AM »
Hi,

I always have a very annoying problem when doing multilayer boards in Altium that I don't know how to get rid of apart from manually patching it with fills.

It happens when I have a multilayer board with internal planes (negative planes moslty used for power and ground), and some unconnected via pattern makes altium generate the mess you see in the attached pic.

It sometimes generates narrow necks too, which aren't detected by the DRC. I'm not sure if I'm doing something wrong or what, but I can't find an automatic solution for the problem, like you have for polygons and such. Any help with this?

Thanks

 

Offline T3sl4co1l

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Re: How do I remove necks and dead copper on internal planes?
« Reply #1 on: January 12, 2017, 04:43:37 AM »
You don't...  |O  Add shapes to the layer manually, to cover the bits.  Make sure to update them if you move things around later.

Better to delete the layer from the stackup, add a Signal Layer in the same position, and use a Polygon to pour it.

Plane layers are also really basic with how they connect (spokes and clearance).  They don't handle oval pads or slot holes. :(

Tim
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Offline dmg

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Re: How do I remove necks and dead copper on internal planes?
« Reply #2 on: January 12, 2017, 09:45:01 AM »
You don't...  |O  Add shapes to the layer manually, to cover the bits.  Make sure to update them if you move things around later.

Better to delete the layer from the stackup, add a Signal Layer in the same position, and use a Polygon to pour it.

Plane layers are also really basic with how they connect (spokes and clearance).  They don't handle oval pads or slot holes. :(

Tim

Damn. Up to this day I used the internal planes and patched the messy areas with fills and stuff, it was a also a reason to check the whole board for potentally starved planes and such. I recently got updated to Altium 17 and got asked to make a minor variant modification for a design to get a new batch of it made. PCB didn't change, but when outputting documentation it said 4 DRC clearance errors. Turns out it was some of the patching fills that for some reason now were considering as stupid violations.

Won't use internal polygons again.
 

Online blueskull

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Re: How do I remove necks and dead copper on internal planes?
« Reply #3 on: January 14, 2017, 08:58:47 PM »
I remember read from somewhere in AD online documentation that they left "plane" feature just for compatibility and they suggest everyone to switch to using internal layers instead.
SIGSEGV is inevitable if you try to talk more than you know.
 

Offline ajawamnet

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Re: How do I remove necks and dead copper on internal planes?
« Reply #4 on: January 16, 2017, 06:03:42 AM »
I've never read anything concerning the removal of neg planes in AD. In fact from what I've seen in AD17 they've added some features for managing planes.

I do a lot of designs with Altium - been an owner since 1995. I do about 130 design a year.

Currently working on a design that has 12 layers with 10 being planes with splits. There's over 82 split planes. If I were to do that with internal polys it'd be a nightmare.

In fact, AD17 has some issues with nested split planes causing hangs in being able to save. Check the Altium forum posts.

As to top/bot pours again I stay away from that. A lot of designers love to add outer layer pours with the idea that it'll somehow aid in EMI emissions and susceptibility. In fact, at the local test lab, we've found it can actually exacerbate radiation due to things like return paths, coupling, etc..

We did a design for a medical device for a leading medical device supplier where one of the engineers wanted us to do outer layer pours. So we did (even stitched it with vias) and the result was just hideous - "... congratulations, that's the highest EMI we've ever seen in the lab" was the comment from testers. When we removed the outer layer copper it passed.

It also creates uncontrolled coplanar wave guides, that for most designs are not an issue but as you get into higher speed signals can have a detrimental effect on impedance. Also on multilayer designs you now have to deal with asymmetric striplines.

There are good reasons to do pours ( as in CPW) and the like, but you really need to know what the topology requires and design to that. Even high-end field solvers/post layout simulators can fail to find issues that can be caused by randomly pouring copper.
 


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