Energy in a PCB flows in the electric and magnetic fields, not in the conductors.
Also need a "nodding" emote here
This is why signal speed is dictated by dielectric constant of the material. A high speed signal appreciatively couples to the ground plane directly below it and generates an immediate opposite current. For anything but very low speed edge rate, this is already kept right near the trace. So a split plane to isolate analog from digital does almost nothing good. But can do plenty bad.
It follows that:
- If you insist on splitting the plane, keep all the traces associated with that region
well within the bounds of the region.- If you ever, EVER run traces over splits, you're going to make an awful mess.
- This applies to 2-layer boards as well: suppose you have ground pour on the top and bottom, and two long traces crossing at right angles. The image of those traces, the negative space they create in the top and bottom pours, behaves in the exact inverse way the traces do. Opening a slit creates a slot antenna (or at low frequencies / impedances, it behaves as an inductance, associated with the length and width of that slot), which couples directly to the trace crossing that slit. At least three vias are required (or four, if you are compulsively symmetric) at this intersection to short together the pours and ameliorate the effect of the slots.
- This doesn't necessarily apply to multilayer boards, if multiple pours are used which overlap for a considerable area. Overlap means relatively high capacitance (or, a low impedance transmission line). You can have traces crossing from one pour to another, so long as those pours are, themselves, well supported above or below by other pours or bypass capacitors.
In analogy to the two-layer ground stitch, the best place for bypass caps between pours is at the edges of the pours, where signal buses cross from one domain to the other. An example might be, a four layer board with signal traces on the top and bottom, a solid ground inner layer, and multiple pours on the second inner layer, say for different voltage domains (3.3V logic, 5V "HV logic", 12V power, etc...). The traces running over the power layer will deliver an image current into the pours on that layer; ideally, the pours should be bypassed to each other, in the places where signals cross them, for best results.
Since the underlying ground is solid, bypass between regions may not be necessary. Signal quality at 3.3 or 5V isn't a big deal anyway: we're talking maybe a single volt, down to fractional volts, for any bounce resulting from these differences -- hardly a concern for "massive" 3 or 5V logic signals!
Note also, differential logic signals don't produce a net image current between planes, if they are routed together and transition at the same time. The trace-to-trace distance need not be small, as long as their transitions cross the plane at about the same time and place. By the way, always treat differential signals as individual lines, first and foremost, including controlled impedance and length matching. The differential coupling between adjacent traces is relatively weak.
From personal experience, I've laid out a high speed 12 bit ADC with LVDS interface, on a board including various 3.3V and 5V logic, and converters for the various supplies required. The ADC section was laid out on one side of the board, digital logic entering one side and analog (including filters and diff buffers) opposite. Solid ground and power (3.3V) planes inside the (4 layer) board, plus extra copper fill (top and bottom) around the ADC section. There was no apparent correlated noise in the system, only a few LSB white noise, attributable to the buffer amp.
If, for some reason, that board had the DC-DC converters beyond the analog side, so all that power had to cross underneath the ADC to reach the rest of the digital stuff, it might've been much worse. I still wouldn't consider splitting the planes (for example, such a layout might be necessary in the case of a very narrow, long board), because noisy signals (like power and CMOS logic buses) can be routed alongside the circuit, away from direct noise. Note that, if the circuit board is laid out one block at a time (ADC here, MCU there, DC-DC over there...), there need not be any signals crossing between regions (they're all bused up and around instead), so the planes could be slotted anyway and it wouldn't make any difference. When your layout follows this approach, you are at the Zen of layout, where you could slot it, but you won't.
There are still plenty of reasons to split planes -- layout should take care of AC, but DC will still follow straight-line paths. Extremely sensitive AC circuits may find residuals as well, especially on a complex board where you can't afford to arrange blocks in a simple (bus or star) arrangement. Even thermal currents can benefit from splitting -- the board itself in this case, not just the copper: very sensitive references are often routed out on three sides, to prevent mechanical stress and thermal gradients from affecting it.
Galvanic isolation is a rather more dramatic example, where your planes are split on all four sides, so the isolated circuit becomes an island of course. This obviously avoids ground loop, but can create EMC issues: the island is a small capacitance (or a lot, if you have a lot of components bridging the isolation -- optos, transformers and so on), which can resonate with cables and such. Common mode ferrite beads and damping components (Y1 type capacitors spanning the barrier, perhaps with ferrite beads or resistors in series) are used to control this electromagnetic situation.
Tim