Trace vs Polygon pour for power rail

[chrischina]

hello,

when designing PCB with altium, we have created a power plane but under the configuration of signal plane so we could divided the plane for different voltage we have. We have some vis that go to top layer of the pcb to power some components. In the power plane I was wondering if it would be better to keep power connection as trace/track or if it is better to have them under the form of surface plane made with polygon ? What are your opinion about it ? Is there any advantages / drawbacks having traces instead of plane or vice versa ?

[T3sl4co1l]

Assuming you're talking about 4 layer design here,

I normally use all signal layers, and add Polygon objects where I want the respective supplies.  Layer 2 (top-middle) is almost always GND, and layer 3 (bottom-middle) is occupied by Polygons spanning VCC, VDD, etc.

There should be no reason to have tracks on inner layers.  If you do, your layout is bad, and you should feel bad.

(I admit I've had a few cases where I needed (signal) traces on an inner layer.  I kept them as short as possible.  It still felt bad, so there.)

There should certainly be no reason to route supplies with traces.  That would defeat the purpose of having a 4-layer board in the first place!

If, instead, you're talking about plane layers, then Tracks and Regions are normally used to divide the negative space into separate net areas.  The remaining conductive regions should be large and wide, just like Polygon pours.

Tim

[ar__systems]

There should be no reason to have tracks on inner layers.  If you do, your layout is bad, and you should feel bad.

I'm hoping you are joking there. There is nothing wrong with having some signal on power layers. Is "not being able to do it any other way" not a good enough reason for you? So what do you do then, switch to 6 layers?

There is no reason NOT to use ground and power layers for signals when you need to.

[T3sl4co1l]

There should be no reason to have tracks on inner layers.  If you do, your layout is bad, and you should feel bad.

I'm hoping you are joking there. There is nothing wrong with having some signal on power layers. Is "not being to do it any other way" not a good enough reason for you? So what do you do then, switch to 6 layers?

There is no reason NOT to use ground and power layers for signals when you need to.

If you've forced yourself to route tracks on an inner layer, after exhausting two whole sides, you're either doing such high density that additional layers (and possibly finer pitch, or HDI construction) are inevitable, or your placement is poor and things can be shoved and turned to simplify the routing.



Tim

[ar__systems]

Looks you are used to a comfortable life of using as many layers as needed without ever touching two power layers Without regard for cost. 

From a practical point of view such position is too restrictive and cant be justified unless you are doing GHz designs.

 

[ajb]

Yeah, there's a whole section of the board complexity spectrum where it makes sense to have two-and-a-half or three routing layers plus a ground plane, but you can't justify 6+ layers or specialty construction.  Sometimes mechanical constraints force a non-ideal layout or just slightly too small an envelope, sometimes the project is just at that level of complexity.

[T3sl4co1l]

But hey, I have yet to run into a board that's,
1. High enough density to need more than 2 layers, and
2. Not so high density that more layers are otherwise unavoidale (e.g., fanout of BGAs), and
3. which couldn't be done on 4 layers, with a minimum of signals on either inner layer.

I've seen plenty of existing designs that used six layers (or more!) when four would be enough, sometimes two would even be enough!

If that means I'm better at placement and routing than you can imagine, or it means my concept of "high enough density" really isn't all that dense, I have no idea. 

Tim

[ar__systems]

I usually start by trying to make things in two layers. That's two layers total, not two + two power planes. On three projects that was not doable and I used 3 or 4 layers.

As you can imagine on two layer board you are bound to route on ground layer unless the design is trivial, does it make it a bad placement/routing from your POV? If not, then why all of a sudden power layers become sacred on 4 layer board? If yes... well if yes, I've got nothing

[T3sl4co1l]

See, now we're getting somewhere

I view a 2-layer board as one ground layer (no power layer, that would be silly) and one routing layer.

Obviously, to route almost anything at all, you need to use both sides (or jumpers).  So the trick is, by pouring both sides with ground, and stitching them heavily, you can get more or less the equivalent to one solid inner layer.

VCC gets routed like any other signal; normally, it's needed to bypass at each component it's routed to.

For additional layers, you get more that can remain solid, and more nets that can be routed that way.  VCC is the next natural candidate; bigger designs with more layers naturally need more supplies, so you always have a good balance.

Tim

[ar__systems]

So the trick is, by pouring both sides with ground, and stitching them heavily, you can get more or less the equivalent to one solid inner layer.

I actually don't like this style of routing. The idea that if you pour everything with copper you'll get superior ground is just wrong. For one thing, on such ground it is next to impossible to figure out the path of return currents, so if you are doing a mixed signal design (analog + digital or digital + high current) you will get quiet analog signals and stable digital part only by luck.

To put this in practical terms, impedance (the only objective measure of quality of the ground plane) of a solid ground plane, and a grid ground plane with 50% copper removed, differ only insignificantly. I don't recall the exact number and source, if I do, I'll post it, but it was like 10%. So trying to keep ground plane a virgin is rather pointless. 

I prefer to have one layer, carefully designed ground, and I don't care if I have to cut into it as long as all return currents go where they should.

[T3sl4co1l]

I actually don't like this style of routing. The idea that if you pour everything with copper you'll get superior ground is just wrong. For one thing, on such ground it is next to impossible to figure out the path of return currents, ...

Again...

I challenge anyone to present an existing 2-layer design, for which I am unable to do precisely those things.

So I still don't know if it's because I'm just this good, or I'm not understanding what you're talking about, but I would love to be given the opportunity to be proven wrong.

Tim

[ar__systems]

What exactly are you asking for - to give you a board for you to do layout?

[T3sl4co1l]

Yeah. Descriptions are mostly useless; a visual transformation would probably emphasize my point better.  But not just any, that would still be easy.  It has to be a particularly "intractable" example,

I actually don't like this style of routing. The idea that if you pour everything with copper you'll get superior ground is just wrong. For one thing, on such ground it is next to impossible to figure out the path of return currents, so if you are doing a mixed signal design (analog + digital or digital + high current) you will get quiet analog signals and stable digital part only by luck.

When I do it, it's entirely by design.  Maybe when others do it, it's by luck, I don't know.  Got any such examples?  I could turn this into a design exercise and exhibit it on my website!

Tim

[ar__systems]

Well I got just just the right example, that I recently gave to an intern to test his skills It is very small, so you are not going to spend more than a day on it, and combines digital, analog, and 2A currents. And it is a real design which I just "unrouted". But it is an eagle file. would you be able to open it? Then we could compare yours and mine

[T3sl4co1l]

Sure Last time I imported Eagle into Altium, it seemed to work out okay.

Tim

[AF6LJ]

Following along this is a good discussion. 

[Mr.B]

Bookmark.

[ar__systems]

Ok, here we go

So few notes: 3 components already on the board can't be moved.
Red square is no-go zone, it is a cutout in the pcb.
Two hall sensors should ideally be placed as close to left as possible (still to the right of the red rect.) However can be moved to the right as necessary to satisfy more important properties.
X2 is input power, 5V.
JP2 is load connector. It can be either 2.5Ohm halogen lamp or LED+resistor.
If it is halogen, we use Q2. Open loop PWM.
If it is LED, we use Q1. Q1 + L2 forms a current source. Current feedback value is taken from R9 and goes into pin 23 of the cpu.
OA-2 of the CPU is used. Max current for LED is 0.6A.
PIN4 is an analog input.

I think that is all required info. I used 8mil/8mil space/line, but I guess 6/6 is also ok, except where wider lines are needed.

[T3sl4co1l]

About two hours later, a teaser:



I cleaned up the schematic to get it more-or-less in line with my preferences.  Cleaned up placement and routing, changed sheet and colors to Altium defaults/preferences.  Didn't edit symbols, because screw that, close enough.



I think it turned out really well.  Single side load.  Everything ended up in neat rows, easily soldered.

The 'analog' stuff is mostly placed and routed along the top.  All the 'mean' switching stuff is on the bottom left.  (JP2's other trace comes back on the bottom side, underneath the visible trace, to minimize radiation. It will be carrying switching current ripple, after all.)  L2-D1-Q1-Q2 is really tight, all in a line, away from the rest.  I'm assuming the hall effect sensor outputs are 'analog', but even if they are strong logic levels, I don't foresee them toggling all that often.  There's no bypass cap for them either (which may be a bit of an oversight, but there's room to put one in).

I could make the board length about 0.4" shorter, without making things much worse.

Also again, I didn't bother editing the new footprints.  Existing ones I pulled from my library, hence the shiny 3D models for most (and real collision checking).

Tim

[ar__systems]

Looks nice, but can't I see the layers. Can you post it? Without it is hard to see what's going on.

[ar__systems]

Are you going to show your bottom layer? Anyway, in the mean time I tried to recreate it. I did not bother doing it completely, just to the point of understanding the topology. It is not quite accurate, but should be close enough to understand what you did.

From what I see, this is exactly kind of problem layout that I expressed my concern about earlier in the thread.  Sure your looks nice and neat, but I don't think it is solid. Expensive tools is not a replacement for skill.

First of all, no bypass on halls. I can't completely know how the power to these two is routed and where it is taken from. Ok, easy to fix. No bypass on PIC? Hmm... I guess C3 is supposed to be that, but look, it is sitting directly on the high current bus. Not good.

Finally, the ground. From the point where Q2 connects to ground, can you show the path that the current will take back to X2? On the ground of such complex shape it is difficult to predict it exactly. But genrally it will flow diagonally, directly towards X2, switching back and forth between top and bottom, or in parallel where possible. So in essence it will flow directly underneath the PIC. This is the worst kind of mistake that an engineer can make (as far as layout is concerned). It creates noisy environment for the CPU to live in. The ADC inputs will be very noisy. Basically you failed to separate ground and power into quiet and noisy areas.

The second pic  is my original layout. Not as a neat and pretty for sure, but you can easily follow the path of high current loop - it will not be crossing CPU. The third pic is just ground. As you can see vertical cuts direct the current flow around the CPU section of the ground.

Any comments are welcome

[Someone]

Any comments are welcome

Great work and thanks for adding all the thoughtful process you followed. Now send both boards out on a cheap prototype service and show the difference in performance?

[Psi]

Need to divide PCB design opinions into three camps

1) If you do X then your PCB is not beautiful and elegant (looks ugly)

2) If you do Y then your PCB may have production issues (bad yield)

3) If you do Z then your PCB may have operational issues (bad grounding etc)

There are two many opinions that are just category 1 and not relevant to get your design working perfectly.

[T3sl4co1l]

^ This.

There is considerable space to vary each parameter, while keeping the others constant (assuming some metric to measure them by).

The PCB designer works within a very large space indeed, and selecting one exact combination of trace positions, routes, sizes and so forth, out of that space, is why it's an art and a science.

Tim

[ar__systems]

Great work and thanks for adding all the thoughtful process you followed. Now send both boards out on a cheap prototype service and show the difference in performance?

I don't need to... I've already seen boards where analog part was very very noisy due to incorrectly laid out ground and the difference that fixing the ground produced. That's for the analog. Re: CPU... making one or two boards is not going to be conclusive in a limited time test. CPU will probably work without problems... until it does not. As in the circuit would rarely misbehave in a non-reproducible ways. If it were purely digital, low speed  circuit - does not matter, you can get away without ground plane at all, routing it as another signal. For high current+analog+digital - lazy ground design will come and bite you from behind.