My issue now is that I am not sure how to analyse circuits with JFETs in them. Can I just take the circuit that I showed and replace the MOSFETs with JFETs? Or are the other concerns that I need to account for?
Yes but:
You need different biasing, which this circuit could stand a change in, anyway.
The first transistor is statically biased, "diode mode", so that it develops a voltage corresponding to how much Vgs is necessary to draw the applied drain current (from the 1k resistor). This voltage is coupled to the bottom transistor, so that it gets the same Vgs, and give or take variation in Id vs. Vds (shouldn't be much), it will carry the same current (i.e., a MOS current mirror).
This works great when the transistors are matched and thermally coupled (as on an IC), but may not work out so well in practice. The transistors at least need to be a matched pair. Since accuracy and power level are not big problems here, thermal matching probably isn't a big deal either (it should be good enough that they're on the same PCB). It's still not the greatest, and wastes a transistor anyway.
I'd rather do it by replacing the transistor "reference" with a simple voltage divider. This is even worse (there's no reference to Vgs at all!), but we do one better by adding an R||C in the source of the bottom transistor. Vg is set such that it's a bit above Vgs(th), and so load current is drawn, causing voltage drop across the source resistor, which reduces Vgs -- negative feedback sets the bias point. The bypass cap ensures the source still "looks" AC-grounded as far as the signal is concerned.
The L-C-L network is a big question, of course. If nothing else, that has to be tuned for the operating frequency. It probably also needs to be tuned for the impedance match (the gate has a fairly high impedance, even at RF). You can solve for that, but it requires having S-parameters or admittance data in the transistor's datasheet; and it'll most likely be different in practice anyway, needing adjustment. The gate L and C should be the most important there; the source L seems out of place, and might be intended to be very small (a fraction of the other L), with the purpose of adding negative feedback at AC or something like that.
Converting this to JFETs means providing Vgs somewhere between negative and 0V (instead of positive), which would stink for directly grounded source -- but in practice, we simply bias the gate at GND and add enough source resistance to let it self-bias again. It's also acceptable to run a JFET at zero gate bias, at least as long as the input signal isn't too strong. The top transistor should have a voltage divider biasing its gate (with bypass to GND), so its Vg is maybe 20-50% of supply. Source voltage will rise above Vg, so that it again sets Vgs by feedback (but Id is still set by the bottom transistor; it's important that Idss of the top transistor be higher than Id of the bottom transistor).
As for "low noise", a cascode might not be ideal, because it basically throws away the gain of one of the transistors -- the main advantage to the circuit is nearly eliminating reverse transfer (gain from output to input). When modest gain and absolute lowest noise is required, it might be better to use a single transistor (common-source or -gate). One advantage of a JFET is, the source input impedance (in common-gate) is fairly modest (it's roughly 1/Gm or Rds(on), which for most will be within a small factor of 50 ohms), and it doesn't need any biasing (again, it can be ran at Vgs = 0). Output impedance essentially gives the gain ratio, so a higher impedance load (100s ohms to a few k) is needed to obtain gain. Which means a matching circuit (LC or wideband transformer is fine).
BJTs are good too. I forget which (BJT, JFET or MOS) is strictly best at 100MHz -- of course, if you need every last dB of noise factor, you can always go with a GaAsFET or PHEMT. Just be careful to use teensy ferrite beads to prevent it from oscillating at stupid-GHz...
Tim
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