That is a very poor design.
The LM324 is being used to buffer the output of the clock generator while providing current limiting. 2N3055, C1061, and then a pair of paralleled 2N3055s are configured as a three stage darlington transistor to get enough current gain.
Problems with this circuit include high dropout of the triple darlington configuration causing excessive heating and low efficiency, overlap of the output clock causing excessive shoot-through current, and poor current sharing of the paralleled output transistors.