2 ADC Integration Questions (Serial communication and crystal oscillator)

[SethGI]

Hi,

I'm designing a board to input four audio signals, amplify them, and run them through an ADC. I have two newbie questions about this. This is the first real board I've designed (I've designed simple arduino shields before) but I'm a high school student with no real electrical engineering training.

1) The chip (ADS1274 by TI) uses SPI for communication. (Frame-sync also available, but I'm using SPI. Everything I've done with SPI in the past has had four pins, SCLK, MISO, MOSI, and SS. This chip doesn't quite. It has DOUT pins as the MISO, and SCLK pin, no MOSI (doesn't matter, probably just means it's a read-only device). But, it doesn't have a SS pin at all. I can't figure out how to use an SPI device that doesn't have an SS pin. There's a DRDY pin that, by their diagrams, seems to send the same signals as the master SS pin usually would. But, since the ADS1274 is obviously a slave device, this isn't helpful. What do I do? Can I just use it without SS???

2) An even more newbie question. The ADS1274 requires a CLK input (no surprise). I just don't know how to wire it up to a device like this. I have embedded crystals on to an ATMega chip before which has two clk-related pins, but the ADS1274 only has one CLK input. How do I connect it?

Thanks for putting up with my dumb questions!

-Seth

[Simon]

1) no idea this may be a bit of an exotic device.
2) the clock comes from the SPI interface on the MCU, it is internally generated, nothing to do with crystals it's just a square wave. It hase to come from the mater in order to keep things syncronised.

[SethGI]

1) no idea this may be a bit of an exotic device.

Ok...

2) the clock comes from the SPI interface on the MCU, it is internally generated, nothing to do with crystals it's just a square wave. It hase to come from the mater in order to keep things syncronised.

Sorry, I should have been more clear. This isn't the SCLK, it's the completely unrelated CLK input for the chip. It does require a crystal oscillator, or some other sort of square wave input.

[JPortici]

typing as i'm looking through the datasheet...

this might help you shred some light. it seems like it uses some kind of semi-spi-semi-i2s protocol, like framed spi on several dspics (that don't have proper i2s)
http://www.microchip.com/forums/m610484.aspx
basically, sck gives the clock, MISO contantly carries data from the ADC to the master and the frame pulse decided where the beginning is

on page 7 of the datasheet, FSYNC pin: Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
which means what i said in frame sync mode. in spi mode it means that you have four/eight new data bytes and you should retreive them ASAP (an irq pin to the master).

for the clock you might use the clock output of your microcontroller, properly divided so it doesn't exceed max clock rate of the ADC

question time: why this part? cirrus logic adcs/codecs are easier to use than this one

[SethGI]

typing as i'm looking through the datasheet...

this might help you shred some light. it seems like it uses some kind of semi-spi-semi-i2s protocol, like framed spi on several dspics (that don't have proper i2s)
http://www.microchip.com/forums/m610484.aspx
basically, sck gives the clock, MISO contantly carries data from the ADC to the master and the frame pulse decided where the beginning is

on page 7 of the datasheet, FSYNC pin: Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
which means what i said in frame sync mode. in spi mode it means that you have four/eight new data bytes and you should retreive them ASAP (an irq pin to the master).

for the clock you might use the clock output of your microcontroller, properly divided so it doesn't exceed max clock rate of the ADC

question time: why this part? cirrus logic adcs/codecs are easier to use than this one

Thanks. To answer your question first, I didn't look to much into the cirrus logic ones. I didn't see any reason that this part would be particularly hard to use, except for this communication bit, which I knew I would be able to work out. This part offers good expandability, is very precise, and guarantees simultaneous sampling which is essential for my application. I just checked out a few cirrus audio datasheets and they all talk about how to synchronize the serial outputs of the chip... but with no guarantee about the synchronization of each sample on all four channels. I am using this to calculate the phase shift of high-frequency audio signals, so synchronous sampling is pretty important it may be overkill, but I don't have a problem with that.

Anyways, thanks for your answer. It makes sense. I guess worst case is this won't be all that plug-and-play and it might take some work to get this sample.

Thanks again for the advice, and I'll definitely take some time to reconsider my part choice.

[rstofer]

Look at the timing diagram on page 8.  DRDY' goes low to tell the master it's time to get with the program and start shifting bits.  The master now has to shift in 24 bits at a rate between 100 kHz and 27 MHz.  However, you need to shift in all 4 channels at the same time so you aren't going to be able to use the SPI gadget of a uC.

See the brief discussion of SPI on page 30.

I know you said that using SPI would be easy but it seems to me like you're going to have to bit-bang the SCK and read/store 4 data pins at some fairly high rate.

I think I would be spending a lot of quality time with the datasheet:

http://www.ti.com/lit/ds/symlink/ads1274.pdf

And, yes, you need to provide a clock.  See Table 6, page 27 and note that, for SPI, you can't use the very highest frequency options.

I would be paying very careful attention to those few paragraphs re: the clock.  Particularly the bit about the 50 Ohm series resistor.  And the bit about using a crystal oscillator.  Note that it doesn't say just a crystal; they want a canned oscillator.

[JPortici]

I would be paying very careful attention to those few paragraphs re: the clock.  Particularly the bit about the 50 Ohm series resistor.  And the bit about using a crystal oscillator.  Note that it doesn't say just a crystal; they want a canned oscillator.

i *think* that if he keeps the distances very small he should be able to provide the clock directly by an MCU clock-out pin. It'll have to be < 27 MHz to keep vdd over 2 volts.... but hell i think he can read too.
it might be easier to deal with only one low jitter clock circuit
also the SPI can be set up so the ADC sends the data separated per channel on four ports.. or cascade them and sends all through data port 1.. i2s like, but depending on the throughput you need you might need to choose a chip with multiple SPI or bit bang it (in assembly/plain C, of course. or you wouldn't have throughput problems anyway.)