my thoughts are:
re 2N3055, yes that's possible because its gain-bandwidth is 1MHz and maybe this is why Chinese kit which uses 2SD1047 works because that Q has bandwidth of 20MHz,
let's have a look at @N3055 data sheet, so it turns out that it has significant storage and delay times which correspond to bandwith. (they must have to)
re follower: ideal follower agree however this follower is darlington pair which stands that it is driven by current, worse for small AC dynamic resistance of B-E diodes should be considered, so more precise model of such follower is, that it has rather small imput imp. (thus draws current) and intrinsic dynamic resistance at input which varies according to operation point Idc in. Very high composite current gain stands for very small input current which makes that dynamic resistance important (dV/dI is large at that point).
re danadak's simualtion.
1 word: oversimplified. (or even too oversimplied)
The schematic was removed important components: Cout = 10uF, Rshunt=0.47R and maybe that 1n4148 protecting Q1,2 from excessive reverse BE voltage.
Lack of Rshunt results in no common voltage to opamp
Cout takes important role in opamp feedback's H(s).
Other constraints are: simple load, while one can use e.g. spice's PWL voltage sources. I enjoy that load I designed which draws from 0 to 3.2A and then returns to 0 rapidly from psu under test. The load is as simple as R=5R, D, and PWL volatge source - this is something hard to get on real test bed.
was there transitional analysis performed or just op. point DC ? we can't see any plots, are there any ?
what was step time for that transitinal simulation ? I meant that some simulations look good unless step is decresed and then results are much worse .. e.g. these oscillations appear. I use 2us for the duration of 190ms and good simulation takes abt 8secs while bad lasts abt 300.
and last word:
here is a claim from one who has real oscillating device. here is my claim regarding my simulation: I can change value of R1 and make the control loop unstable or solid stable no matter how many pF capacitors will add to voltage divider. Moreover my simulation is realistic because power Q is supplied from DC 33V + AC (8Vpp, 100Hz) compound voltage and load is dynamic.
while another one claims that the loop is stable because he made "simulation" which is just incomplete. (I thought "stupid")
Question: how much such claim is worth ?
regarding simulations, device models and "simulations" I suggest to see (and understand) this thread:
http://www.diyaudio.com/forums/solid-state/5493-pspice-models-2955-3055-a-2.htmlit was not an accident that for simulation I used these components which I used. I can rely on models for these devices. (verified "in the field")