7 Segment Display Driver for Hexadecimal

[Legion]

I was looking for an IC that would drive a 7 segment display with hex digits. I haven't been able to find any that are still made though. It's strange because they have 4 inputs, but the datasheets show no support for digits above 9. From google searches it looks like people use microcontrollers now, but I was hoping to do it with logic ICs.

Just seems like there's no reason that ICs like the 4511 couldn't display A - F.

[edavid]

TIL311
Fairchild 9368, 9369, 9370, 9374
MC14493, MC14494, MC14495
MM74C917
ICM7218

Oops, missed the "still made".  Guess that just leaves the ICM7218, which is probably not what you want 

Good opportunity to learn how to use PLDs?

[David Hess]

The old standby is the 7447 series but of course they do not decode hexadecimal.  Some dedicated LED display drivers do though.  Maxim makes some.

You could also program a small EPROM or programmable logic device to do the decoding.  Either could even implement leading zero blanking.  The lowest cost solution might be to program a PIC microcontroller to do it.

[denelec]

The lowest cost solution might be to program a PIC microcontroller to do it.

A agree with the microcontroller solution.  They are very cheap and you can configure the inputs and outputs to suit your needs.
If you are not familiar with the PICs, you can buy a PICAXE.
http://www.picaxe.com/
They are PIC microcontrollers programmable in simple, very easy to learn, BASIC language.  They are relatively cheap and you can learn to use them in a few hours.

[Macbeth]

Microcontroller and use multiplexing.

ETA: Too much PIC fanbois on this thread - consider AVR (or Arduino) instead. 

I feel I must point out Daves old rant here: http://www.eevblog.com/2010/02/22/eevblog-63-microchip-pic-vs-atmel-avr/ 

[denelec]

Microcontroller and use multiplexing.

ETA: Too much PIC fanbois on this thread - consider AVR (or Arduino) instead. 

I feel I must point out Daves old rant here: http://www.eevblog.com/2010/02/22/eevblog-63-microchip-pic-vs-atmel-avr/ 

If you already know the AVR/Arduino, then it's the best choice.
For such a simple task, the best microcontroller will be the one requiring the least investment in time (learning curve) and money.

[N2IXK]

Any insight into why the 7447/7448 weren't made to handle A-F outputs?  Did every manufacturer provide the same output definitions for A-F inputs. National's datasheet shows that the chip DOES provide unique output patterns, just not ones that produce A-F displays on a 7 segment display.

[David Hess]

If you already know the AVR/Arduino, then it's the best choice.
For such a simple task, the best microcontroller will be the one requiring the least investment in time (learning curve) and money.

And the one with the correct packaging and minimum external support.  An AVR by itself would certainly qualify but not the whole Arduino board.

[David Hess]

Any insight into why the 7447/7448 weren't made to handle A-F outputs?  Did every manufacturer provide the same output definitions for A-F inputs. National's datasheet shows that the chip DOES provide unique output patterns, just not ones that produce A-F displays on a 7 segment display.

I remember asking that question in the past and getting an answer but I no longer recall what it was.  There was some justification but it may have just been "simplicity".

What I wonder now is why there was no alternative 4 bit binary to 7 segment hexadecimal decoder driver with a different TTL part number.

I see that someone has done this with a PIC:

http://picprojects.org.uk/projects/decoder7/

[free_electron]

come come. really ? microprocessors ?
take a simple pal or gal. 16v8 can do it without blinking.

the reason for the wonky patterns is that it greatly reduced logic . the extra patterns are simply random 1 or 0.
when minimising the equations using a karnaugh map you could fill in whatever and flip those to 1 or 0 to maximise the size of the clouds in the map.

in those early chips every transsitor counted

[edavid]

What I wonder now is why there was no alternative 4 bit binary to 7 segment hexadecimal decoder driver with a different TTL part number.

I already mentioned the Fairchild 9368, 9369, 9370, 9374 TTL parts...

[David Hess]

What I wonder now is why there was no alternative 4 bit binary to 7 segment hexadecimal decoder driver with a different TTL part number.

I already mentioned the Fairchild 9368, 9369, 9370, 9374 TTL parts...

Did anybody ever second source them?  I do not remember them being readily available so it was easier to roll our own.

[David Hess]

come come. really ? microprocessors ?
take a simple pal or gal. 16v8 can do it without blinking.

They sure can but a PIC is less expensive and you could program it to generate a self timed multiplexed display and use the serial interface of your choice.

the reason for the wonky patterns is that it greatly reduced logic . the extra patterns are simply random 1 or 0.
when minimising the equations using a karnaugh map you could fill in whatever and flip those to 1 or 0 to maximise the size of the clouds in the map.

in those early chips every transsitor counted

I was considering drawing up a Karnaugh map to see if that was the reason.

[Legion]

I was hoping to use this as an opportunity to mess around with logic ICs. Looks like it may not be possible unless I can find some NOS or pulls.

[miguelvp]

I was hoping to use this as an opportunity to mess around with logic ICs. Looks like it may not be possible unless I can find some NOS or pulls.

You can do it with logic IC's down to the metal.
At the bottom of the post is the logic table from 0 to 15 and the segments that must be on.

Usually for this type of problems you have the input and the inverse of the inputs as 8 lines into the circuit.
Then do logic per segment. You can use not, and, or, nand, nor, xor, nxor, buffer the result via flip-flops and the output can be inverted if it makes more sense to turn segments off instead of on at the end.

Look for the less cases, for example segment a is off if
not((not i3) and (not i2) and (not i1)) and (i0)

xor ? or ?

not((not i3) and (not i1) and (not i0)) and (i2)

xor ? or ?

not((not i2) and (not i1)) and (i3) and (i0)

xor ? or ?

(not i2) and (i3 and i1 and i0)

xor ? or ?

(not i0) and (i3 and i2 and i1)


But this will require some gates and a lot of thinking

To get you started here is the truth table that you must achieve.
Then again you can always get a chip that does it for you

Code: [Select]

in   abcdefg
0000 1111110
0001 0110000
0010 1101101
0011 1111001
0100 0110011
0101 1011011
0110 0011111
0111 1110000
1000 1111111
1001 1110011
1010 1110111
1011 0011111
1100 1001110
1101 0111101
1110 1001111
1111 1000111

 
  - a
f| |b
g -
e| |c
  - d
[code]


[Legion]

You can do it with logic IC's down to the metal.
At the bottom of the post is the logic table from 0 to 15 and the segments that must be on.

Usually for this type of problems you have the input and the inverse of the inputs as 8 lines into the circuit.
Then do logic per segment. You can use not, and, or, nand, nor, xor, nxor, buffer the result via flip-flops and the output can be inverted if it makes more sense to turn segments off instead of on at the end.

Look for the less cases, for example segment a is off if
not((not i3) and (not i2) and (not i1)) and (i0)

xor ? or ?

not((not i3) and (not i1) and (not i0)) and (i2)

xor ? or ?

not((not i2) and (not i1)) and (i3) and (i0)

xor ? or ?

(not i2) and (i3 and i1 and i0)

xor ? or ?

(not i0) and (i3 and i2 and i1)


But this will require some gates and a lot of thinking

To get you started here is the truth table that you must achieve.
Then again you can always get a chip that does it for you

Code: [Select]

in   abcdefg
0000 1111110
0001 0110000
0010 1101101
0011 1111001
0100 0110011
0101 1011011
0110 0011111
0111 1110000
1000 1111111
1001 1110011
1010 1110111
1011 0011111
1100 1001110
1101 0111101
1110 1001111
1111 1000111

 
  - a
f| |b
g -
e| |c
  - d
[code]


Alright. Sounds like fun. I have a bunch 7400 and 4000 series chips laying around, should be able to do it.

[miguelvp]

cool 

I did simplify the logic for segment a in this crude LTspice schematic.



Edit: of course this wont light the led, it's just to demonstrate the logic, since the model only outputs about 790mv when on.

[edavid]

I don't think gates are the right way to go here - you could at least use 74151s.  You could also start with a 7447 or 74247 and just fix up the incorrect outputs - I think that would save a couple of packages.  If you use a 7447, don't forget to add the tails on the 6 and 9.

[SL4P]

Where is the hex data coming from?
If already a micro - you could pump it out to a shift register - to drive the 7-segments from a '595 or similar... ?!

[David Hess]

I might use a 74154 4-to-16 line decoder or pair of 74138 3-to-8 line decoders and an array of transistors.

[miguelvp]

True that, if the BCD to 7 segment turns off the segments for cases A-F, then you can use the 0-9 of a decimal 7 segment and add the logic decoding for the A-F cases.

On an FPGA you can just draw this using minimal fabric, but that's overkill.

But learning how to deal with this things directly at the gate level, even if not efficient is really fun and educational, and maybe even frustrating enough to feel empowered when it finally works.

[GK]

You don't need any gates to decode from decimal to 7-segment. That can be done just with diodes. For example:

[MLXXXp]

Coincidentally, but a bit off topic: Yesterday, while looking through my parts for something else, I came across some HP 5082-7340 hex LED displays, unopened in the original packaging.
http://web.mit.edu/6.s28/www/datasheets/HP_led_display.pdf
I'll have to come up with some use for them.

[Legion]

You don't need any gates to decode from decimal to 7-segment. That can be done just with diodes. For example:

That would be a lot of diodes.

[David Hess]

You don't need any gates to decode from decimal to 7-segment. That can be done just with diodes. For example:

That would be a lot of diodes.

78 by my count but I would use transistors.  You end up with something like this but larger:

[miguelvp]

You don't need any gates to decode from decimal to 7-segment. That can be done just with diodes. For example:

That would be a lot of diodes.

78 by my count but I would use transistors.  You end up with something like this but larger:

76 actually

Code: [Select]

in   abcdefg
0000 1111110 6  6
0001 0110000 2  8
0010 1101101 5 13
0011 1111001 5 18
0100 0110011 4 22
0101 1011011 5 27
0110 0011111 5 32
0111 1110000 3 35
1000 1111111 7 42
1001 1110011 5 47
1010 1110111 6 53
1011 0011111 5 58
1100 1001110 4 62
1101 0111101 5 67
1110 1001111 5 72
1111 1000111 4 76
But if you reverse the logic i.e. turn the segment off instead of on then you'll end up with 36 of them. And you still need a 4 to 16 line decoder.

Code: [Select]

in   abcdefg
0000 1111110 1  1
0001 0110000 5  6
0010 1101101 2  8
0011 1111001 2 10
0100 0110011 3 13
0101 1011011 2 15
0110 0011111 2 17
0111 1110000 4 21
1000 1111111 0 21
1001 1110011 2 23
1010 1110111 1 24
1011 0011111 2 26
1100 1001110 3 29
1101 0111101 2 31
1110 1001111 2 33
1111 1000111 3 36

The 74154 will take care of all the input decoding like David suggested. Also a single 74138 combined with a BDC chip 0-9 will greatly reduce the number of chips and you can focus on 1010 to 1111 (A to F).

Using logic gates you endup building a 74154 anyways. I was going to post the full thing but it was late and I'm at work now so the file is at home.

But pretty much I ended up with a 4 to 16 line decoder implemented with 4 inverters, 16 AND gates (4 inputs ones) just to decode the input. For the segments I ended up with about 7 nor gates some using up to 5 inputs some not and 3 OR gates for the 0,8 & A that needed more than 5 inputs.

But it can be optimized further.

Again an existing BDC 7 segment chip combined with a 3 to 8 line decoder (74138) and some logic gates will be the most ideal thing for number of chips.

Edit, on the 3 to 8 line decoder you will have to use the most significant bit to drive the chip enable, then the other 3 bits for the inputs. Then combine the outputs of the BDC 7 segment outputs with this outputs to handle A to F.

[David Hess]

76 actually.

But if you reverse the logic i.e. turn the segment off instead of on then you'll end up with 36 of them. And you still need a 4 to 16 line decoder.

I was not being real rigorous in my count but inverting the logic to make it 36 is a great idea.

The 74154 will take care of all the input decoding like David suggested. Also a single 74138 combined with a BDC chip 0-9 will greatly reduce the number of chips and you can focus on 1010 to 1111 (A to F).

Using logic gates you endup building a 74154 anyways. I was going to post the full thing but it was late and I'm at work now so the file is at home.

But pretty much I ended up with a 4 to 16 line decoder implemented with 4 inverters, 16 AND gates (4 inputs ones) just to decode the input. For the segments I ended up with about 7 nor gates some using up to 5 inputs some not and 3 OR gates for the 0,8 & A that needed more than 5 inputs.

But it can be optimized further.

Again an existing BDC 7 segment chip combined with a 3 to 8 line decoder (74138) and some logic gates will be the most ideal thing for number of chips.

Edit, on the 3 to 8 line decoder you will have to use the most significant bit to drive the chip enable, then the other 3 bits for the inputs. Then combine the outputs of the BDC 7 segment outputs with this outputs to handle A to F.

Since the 74138 has both positive and negative chip enables, two can be trivially combined to make one 4 to 16 line decoder.  I would do that simply because 2 16-pin DIPs are more conveneint than 1 double wide 24-pin DIP.  There is also a 74138 variation in the 74237 which includes input latches.

[Macbeth]

Coincidentally, but a bit off topic: Yesterday, while looking through my parts for something else, I came across some HP 5082-7340 hex LED displays, unopened in the original packaging.
http://web.mit.edu/6.s28/www/datasheets/HP_led_display.pdf
I'll have to come up with some use for them.

They look fantastic!

[miguelvp]

So, here is the logic only decoder, that can probably be optimized.

As you can see, the input part is really a 4 to 16 line decoder.

Implementing just the decoder on a PSoC 4200 from cypress takes 16 macrocells on the programmable logic, but for a buck a chip might be worth it and ignore that it's an 32 bit ARM cortex M0 processor
I might be able to implement the or gates too and just do a direct solution and you'll have a 32 bit risc processor as a bonus

Code: [Select]

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital clock dividers        :    0 :    4 :    4 :   0.00%
Pins                          :   22 :   14 :   36 :  61.11%
UDB Macrocells                :   16 :   16 :   32 :  50.00%
UDB Unique Pterms             :   16 :   48 :   64 :  25.00%
UDB Total Pterms              :   16 :      :      :
UDB Datapath Cells            :    0 :    4 :    4 :   0.00%
UDB Status Cells              :    0 :    4 :    4 :   0.00%
UDB Control Cells             :    0 :    4 :    4 :   0.00%
Interrupts                    :    0 :   32 :   32 :   0.00%
Comparator/Opamp Fixed Blocks :    0 :    2 :    2 :   0.00%
SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%
CSD Fixed Blocks              :    0 :    1 :    1 :   0.00%
8-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
7-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
Temperature Sensor            :    0 :    1 :    1 :   0.00%
Low Power Comparator          :    0 :    2 :    2 :   0.00%
TCPWM Blocks                  :    0 :    4 :    4 :   0.00%
Serial Communication Blocks   :    0 :    2 :    2 :   0.00%
Segment LCD Blocks            :    0 :    1 :    1 :   0.00%

Then again a 74HC154 will be a fraction of that cost for the decoder.

On another post I'll simplify the input using a BCD to 7 segment chip and using a 3 to 8 line decoder to deal with the A to F digits. The important thing about the BCD to 7 segment is that for invalid values it has to display blank, some actually drive the segments at values past 9.

Edit: I wired 3 backwards it turns off segments e & f instead of b & c.

[GK]

4-to-16 decoding with diodes and transistors.

Schematic:

https://www.eevblog.com/forum/projects/home-brew-analog-computer-system/?action=dlattach;attach=35298

Vid:

[miguelvp]

Ok, so the 74HC4511 BCD to 7 segment latch/decoder and driver sets the a-g segments high. Edit: Note this chip actually leaves the segments blank for values past 9, not all of them do, so be careful what BCD to 7 segment chip you get.
http://www.ti.com/lit/ds/symlink/cd74hc4511.pdf
The SN74AHC138 3 to 8 decoder set the line low for the value and we only care about the higher combinations 1010 to 1111

http://download.siliconexpert.com/pdfs/2014/2/5/20/15/43/27/txn_/manual/554sn54ahc138.pdf

So you have to invert the outputs and Y1 is meaningless since it belongs to the input value 9 so it can be ignored.

Here is a picture of what it would be:

But I haven't run the simulation and the spice model is not complete since I didn't want to model the 74HC4511, and I took liberties modeling the SN74AHC138, Also you will need a latch on the inverters, but so you can get the gist.

Edit, note on the picture that G2a and G2b have to be forced low, or inverse G1 to drive those pins.

Edit2 to clarify the output from SN74AHC138:

Code: [Select]

Y2 = A
Y3 = B
Y4 = C
Y5 = D
Y6 = E
Y7 = F

I think a_bcd to g_bcd might need Not gates or at least e_bcd. not going to go through the details to debug it. But it should be around:
6 NOR gates
7 OR gates
6 NOT gates (and maybe 7 more or one more for e_bcd)
And you want to latch the SN74AHC138 outputs

Yeah, I think e_bcd has to be inverted for that to work. oops.
Edit: modified the image to reflect the changes and polished up the 3 to 8 line decoder too

Edit again: The 74HC4511 outputs have to be inverted for that circuit to work. But it shows how you can combine a 10 digit BCD to 7 segment with a 4 to 8 line decoder plus a bit of logic to make a binary coded hexadecimal 7 segment driver.

[miguelvp]

4-to-16 decoding with diodes and transistors.

Cool, that was probably fun to build!

[miguelvp]

So I was bored and opened my PSoC Creator and saw the decoder, so I figured that I'll give it a try and implement the whole thing in the programmable logic of the PSoC4 4200 prototyping kit that I got for $4 from Cypress.


http://www.cypress.com/?rID=92146

On top of being an ARM 32-bit Cortex M0 it has four programable UDBs with 8 macro cells each or 32 total macrocells. Also LCD drive is supported on all pins (common or segment).

So I went ahead and made modules for the 4-line to 16 line decoder and for the Hex to 7 segment display.

The top design ended up as this:


The 4-line to 16-line decoder implementation (24 AND gates and 4 NOT gates):


And the 16-line to Hex 7 segment driver ended up like this (7 NOR gates and 22 OR gates):


Edit: Fixed the decoder since it was wired to display E instead of 3

Total resources used, 13 pins, 7 macrocells out of 32 total & 20 Pterms out off 64 total.

Code: [Select]

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital clock dividers        :    0 :    4 :    4 :   0.00%
Pins                          :   13 :   23 :   36 :  36.11%
UDB Macrocells                :    7 :   25 :   32 :  21.88%
UDB Unique Pterms             :   20 :   44 :   64 :  31.25%
UDB Total Pterms              :   27 :      :      :
UDB Datapath Cells            :    0 :    4 :    4 :   0.00%
UDB Status Cells              :    0 :    4 :    4 :   0.00%
UDB Control Cells             :    0 :    4 :    4 :   0.00%
Interrupts                    :    0 :   32 :   32 :   0.00%
Comparator/Opamp Fixed Blocks :    0 :    2 :    2 :   0.00%
SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%
CSD Fixed Blocks              :    0 :    1 :    1 :   0.00%
8-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
7-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
Temperature Sensor            :    0 :    1 :    1 :   0.00%
Low Power Comparator          :    0 :    2 :    2 :   0.00%
TCPWM Blocks                  :    0 :    4 :    4 :   0.00%
Serial Communication Blocks   :    0 :    2 :    2 :   0.00%
Segment LCD Blocks            :    0 :    1 :    1 :   0.00%

Now I have to find me a 7 segment display to test it. I do have an FPGA dev board that could output the counters and then get the connect the GPIO to one of the 7 segment displays in there. If I do that I'll take a picture and post it.

I could also put the counter on the prototype board, after all it has a 32bit processor and I have 23 free pins.

You can get the chip itself for just $1 from them and one single chip could probably drive 2 7 segment displays, a bit of overkill but it's so cheap!
It also support PWM so it can be altered to support intensity variation of the displays as well.

[GK]

How about just using a LUT?

http://www.cypress.com/?rID=46472

4 lines in (BCD), 7 lines out.

[miguelvp]

That will work too it does use one more unique pterm

Code: [Select]

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital clock dividers        :    0 :    4 :    4 :   0.00%
Pins                          :   13 :   23 :   36 :  36.11%
UDB Macrocells                :    7 :   25 :   32 :  21.88%
UDB Unique Pterms             :   21 :   43 :   64 :  32.81%
UDB Total Pterms              :   25 :      :      :
UDB Datapath Cells            :    0 :    4 :    4 :   0.00%
UDB Status Cells              :    0 :    4 :    4 :   0.00%
UDB Control Cells             :    0 :    4 :    4 :   0.00%
Interrupts                    :    0 :   32 :   32 :   0.00%
Comparator/Opamp Fixed Blocks :    0 :    2 :    2 :   0.00%
SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%
CSD Fixed Blocks              :    0 :    1 :    1 :   0.00%
8-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
7-bit CapSense IDACs          :    0 :    1 :    1 :   0.00%
Temperature Sensor            :    0 :    1 :    1 :   0.00%
Low Power Comparator          :    0 :    2 :    2 :   0.00%
TCPWM Blocks                  :    0 :    4 :    4 :   0.00%
Serial Communication Blocks   :    0 :    2 :    2 :   0.00%
Segment LCD Blocks            :    0 :    1 :    1 :   0.00%

I also wanted to create the modules for other uses. but yeah, the LUT is way easier.

[Witention]

I searched on google for this, but I only can find references to DM9368. This IC is perfect, because I wan't it to have leading zero blanking. But I'm afraid this IC is not being manufactured.

Is it there a replacement IC that does the same thing, especially from the 74HC family?

[miguelvp]

I searched on google for this, but I only can find references to DM9368. This IC is perfect, because I wan't it to have leading zero blanking. But I'm afraid this IC is not being manufactured.

Is it there a replacement IC that does the same thing, especially from the 74HC family?

If you don't mind paying $17 per chip (or $13 qty 4) or ask for a quote to the other supplier that has 800 of them:
http://www.findchips.com/search/DM9368

But you can use PSoC with minor modifications to add a chip select so when it's not it's blanked.
You might be able to fit 3 segments per chip, maybe just 2.
But the PSoC 1 and PSoC 3 has more digital blocks so one chip might do it.