74HC193 and Negative Numbers

[bitshift]

Hey guys,

I need a 4 bit up/down counter to count the pulses of a rotary encoder. I want to use a 74HC193 (datasheet).

If you pulse the count up pin, the counter adds 1 to the count. If you pulse the count down pin, the counter removes 1 from the count. This is simple enough but the part I can't seem to figure out is what happens if the count is at 0 and you pulse the count down pin?

I would breadboard this and test but unfortunately the shops are closed and I won't be able to get hold of the IC for a few days.

[Ian.M]

When counting down, it wraps around from 0x0 to 0xF.  Similarly when counting up it wraps from 0xF to 0x0.  It has to be that way for the /TCU and /TCD outputs to be usable for cascading 74xx193 chips to make a multi-digit counter.

[Simon]

I'm not sure to be honest, I would expect either of two things (I don't have time to read the datasheet right now), either is just stops at 0 or it starts to count down going from 0000 to 1111 and then 1110 and then 1101 etc.

I think the solution you need is to start at 1000 so that you have room to count either way, which is sort of how positive and negative numbers are dealt with in computers.

A thorough read of the datasheet may reveal some clues to the counters operation.

[bitshift]

Perfect thanks all 

[retrolefty]

The 74HC193 is a 4 bit binary counter, it knows no negative (2s complement) convention, just 4 bit counts with underflow/overflow/ or carry/borrow if you like. It counts a range count of binary 0 to 15, all positive values. Negative binary numbers requires a different count method where the high order bit is a sign bit rather then a value bit and requires a different carry/borrow method.

 Up and down is not the same as negative and positive. Just like C/C++ has separate unsigned and signed integer number representation. 0x8001 represents two different values depending on if it's binary value (unsigned) or a 2s complement value (signed).



 

[Ian.M]

The O.P's linked datasheet explicitly gives the wraparound sequences as annotations on Fig.8.
It also gives the cascaded counter configuration as Fig.17.

The 74HC193 is a 4 bit binary counter, it knows no negative (2s complement) convention, just 4 bit counts with underflow/overflow/ or carry/borrow if you like. It counts a range count of binary 0 to 15, all positive values. Negative binary numbers requires a different count method where the high order bit is a sign bit rather then a value bit and requires a different carry/borrow method.

You are mistaken.  Consider 2x 74xx193 chips connected in the Fig.17 cascaded configuration.
 
Initially reset them to 0x00, with all control inputs high, then take MR low.
Apply one low going pulse to CPD. 
As the first stage (low nibble) contains 0b0000, the pulse on CPD will propagate to /TCD
On the rising edge of the pulse, both counters will therefire decrement to 0xFF.

0xFF is -1 in 2's compliment arithmetic.

The only thing you have to fudge is an overflow flag.  If the top bit of the cascaded chain of counters toggles without a /TCU or /TCD pulse out from that counter, your twos compliment count has overflowed.

[T3sl4co1l]

If you want saturating arithmetic (decrement stops at 0 or whatever floor value; increment stops at 10 or 15 or whatever ceiling value), you need a logic gate or digital comparator to prevent disable the respective clock direction.

Tim

[Brumby]

The 74HC193 is a 4 bit binary counter, it knows no negative (2s complement) convention, just 4 bit counts with underflow/overflow/ or carry/borrow if you like. It counts a range count of binary 0 to 15, all positive values.

There is no 'sign' involved here - but you've already negated this argument with this statement:

Up and down is not the same as negative and positive.

They're only positive values if you define the data structure as unsigned.  It would be better to describe this chip as following a binary sequence.  In that, there is no ambiguity.  The ones and zeroes simply follow a logical pattern.

The consideration of positive and negative with a 'sign' only comes from how those ones and zeroes are viewed.  The internal computational method of 'two's complement' is used purely for efficiency, based on a range of positive and negative numbers being symmetric around zero.  This chip - singly or cascaded - has no need to have any regard for a sign, but the outputs could be interpreted any way the designer wants.

[retrolefty]

The 74HC193 is a 4 bit binary counter, it knows no negative (2s complement) convention, just 4 bit counts with underflow/overflow/ or carry/borrow if you like. It counts a range count of binary 0 to 15, all positive values.

There is no 'sign' involved here - but you've already negated this argument with this statement:

Up and down is not the same as negative and positive.

They're only positive values if you define the data structure as unsigned.  It would be better to describe this chip as following a binary sequence.  In that, there is no ambiguity.  The ones and zeroes simply follow a logical pattern.

The consideration of positive and negative with a 'sign' only comes from how those ones and zeroes are viewed.  The internal computational method of 'two's complement' is used purely for efficiency, based on a range of positive and negative numbers being symmetric around zero.  This chip - singly or cascaded - has no need to have any regard for a sign, but the outputs could be interpreted any way the designer wants.

 I 100% agree and that was the point I was trying to make, perhaps poorly. I was concerned about the word negative used in the posting title. I was trying to see if the OP understood what you clearly explain. 

[bitshift]

Understood clearly, thank you everyone 

For my application I am trying to count the number of pulses created by a rotary encoder. This needs to include direction. It turns out that since the 74xx163 wraps over to 0b1111 when decremented from 0, I can just interpret the value as being signed. Naturally the number of pulses that can be counted is divided by two but this should be acceptable. I will certainly test once I get hold of an IC.

[SL4P]

Just for curiosity - I know there are good reasons to use hardware, but for many applications and the same price, you could use a 50 cent uP to do the same thing - with exactly the preferred output you need.

[bitshift]

One is for learning to create digital circuits and another is that micros are expensive here in South Africa. My application has a lot of I/O so saving pins is important. There are 3 rotary encoders and 16 buttons that make up the user interface.

[SL4P]

Good answer!
Just for the record...in fancier pro equipment, they often dedicate a separate 'front panel' controller to achieve this - which also offloads the encoders, display refreshes from the main processor.

[Brumby]

The 74HC193 is a 4 bit binary counter, it knows no negative (2s complement) convention, just 4 bit counts with underflow/overflow/ or carry/borrow if you like. It counts a range count of binary 0 to 15, all positive values.

There is no 'sign' involved here - but you've already negated this argument with this statement:

Up and down is not the same as negative and positive.

They're only positive values if you define the data structure as unsigned.  It would be better to describe this chip as following a binary sequence.  In that, there is no ambiguity.  The ones and zeroes simply follow a logical pattern.

The consideration of positive and negative with a 'sign' only comes from how those ones and zeroes are viewed.  The internal computational method of 'two's complement' is used purely for efficiency, based on a range of positive and negative numbers being symmetric around zero.  This chip - singly or cascaded - has no need to have any regard for a sign, but the outputs could be interpreted any way the designer wants.

 I 100% agree and that was the point I was trying to make, perhaps poorly. I was concerned about the word negative used in the posting title. I was trying to see if the OP understood what you clearly explain. 

My apologies for not picking up on that.  I think i need to upgrade my binary thinking to tri-state.

[Ian.M]

If its a quadrature encoder, there are all sorts of ways of getting the interface to an up/down counter wrong, and very few ways of getting it right.   The simplistic approach of using one channel as the counter clock and sampling the other to determine the direction fails badly if the active edge of the clock is noisy, and can easily lead to counter runaway if the clock channel jitters.    You can add on various debouncing strategies, but in the end, you end up with a metric buttload of logic and monostables replacing one MCU programmed with a state machine based quadrature encoder counter.   An indication of the difficulties involved are the number of manufacturers who offered competing QEI => up/down counter interface chips.