74LS pull up switch configuration.

[MsJaye]

Hello everyone,

I've been working on a project, and wanted a check on what I'm planning to implement.

I've got a signal line running from the output of one 74LS device to the input of another 74LS device. I want to keep the signal line as short as possible. I also want to be able to use a switch to make the signal line either always high, or driven by the 74LS output.

Here's what I was thinking:


                    ^ +5V     
                    |     
                    |     
                     /  Switch
                    /
                    |     
           1k       |      1k
OUT >-----/\/\/-----+-----/\/\/----->IN


Does this make any sense? Is there some simpler way to do this that I've missed? It seems as though it should be obvious.

I don't want to have the switch in-line with the signal, as it will be mounted on a front panel, and the wires will get quite long.

Many thanks,
Jaye.

[newbrain]

If you're working with actual LS TTL, this is not a nice solution.
Noise immunity will be greatly reduced, especially at digital low level.

If you check e.g. the 74LS00 datasheet (http://www.ti.com/lit/ds/symlink/sn5400.pdf, page 5), you can see that the input current at low,  IIL is in the order of 400µA.
Across 2kohm resistor that makes 800mV.
Guaranteed output low VOL is 0.4V, plus the drop across R: 0.4V + 0.8V = 1.2V.
Guaranteed maximum input voltage for low is 0.8V < 1.2V...doesn't look good.
For high level, it should work (IIH = 20µA -> 40mV drop).

The correct way to do it should be to use a couple of spare gates (NORs or NANDs), with one input connected to the switch, see the (horribly crude) drawing attached; for the NOR case, the switch should go on the first gate, and its action would be reversed.
Of course if you have a spare OR you need a single gate!

This will introduce a delay of about 16ns, that can or cannot be tolerable in your design (if you need to keep the track short, there might be a reason...). Not that resistors in the path would not affect dynamic characteristics, though.

[MsJaye]

Mm. That was exactly what I wanted explained, thanks.

I'll try to switch some parts over to 74F to grab a few extra nanoseconds: then I'll be able to insert those OR gates.

Jaye.

[grumpydoc]

Mm. That was exactly what I wanted explained, thanks.

I'll try to switch some parts over to 74F to grab a few extra nanoseconds: then I'll be able to insert those OR gates.

Jaye.

74F is heavy on power - 74ALS (5ns) or 74HC(T)(6ns at 5.0V VCC) would be better

Also why run through so many gates? Just run through a 74xx32 with one input switched low/high and the other with the signal that you want. You might want to think about some debounce on that switch anyway.

Finally, why is the timing so tight - having a design that will be affected by a single gate delay sounds a bit tight to be reliable in practice.

[newbrain]

Also why run through so many gates? Just run through a 74xx32 with one input switched low/high and the other with the signal that you want. You might want to think about some debounce on that switch anyway.

Of course! (and I suggested it too) But, in my experience, I always ended up with some spare NAND, NOR or Not, rather than non-inverting logic gates...
And debouncing, no doubt.

Also, if the design is so sensitive, maybe a synchronous, glitch free, way of gating the signal would be even better (but we don't know, is that a clock, data, control?).

I mostly wanted to point out the issues with the resistor based solution.

[eetech00]

The answer may seem obvious...but I'll ask anyway...what type of switch will you use? Toggle? Pushbutton?