Found some VHDL from when I was simulating the Cinematronics CPU, the formating didn't come out to well.
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-- Company:
-- Engineer:
--
-- Create Date: 12:56:53 03/31/2009
-- Design Name:
-- Module Name: S181 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity S181 is
port ( cn : in std_logic;
m : in std_logic;
s : in std_logic_vector (3 downto 0);
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
fout : out std_logic_vector (3 downto 0);
c4 : out std_logic;
Xout : out std_logic;
Yout : out std_logic;
eq : out std_logic);
end S181;
architecture Structural of S181 is
signal f3,f2,f1,f0 : std_logic;
signal h3,h2,h1,h0 : std_logic;
signal i3,i2,i1,i0 : std_logic;
signal nm,x,y : std_logic;
signal x3,x2,x1,x0 : std_logic;
signal z3,z2,z1,z0 : std_logic;
signal nb3,nb2,nb1,nb0 : std_logic;
signal alu_13 : std_logic;
signal alu_45 : std_logic;
signal alu_55 : std_logic;
signal alu_58 : std_logic;
signal alu_61 : std_logic;
signal alu_64 : std_logic;
signal alu_66 : std_logic;
signal alu_68 : std_logic;
signal alu_70 : std_logic;
signal alu_72 : std_logic;
begin
h3 <= not(((s(2) and nb3) or (s(3) and b(3))) and a(3));
h2 <= not(((s(2) and nb2) or (s(3) and b(2))) and a(2));
h1 <= not(((s(2) and nb1) or (s(3) and b(1))) and a(1));
h0 <= not(((s(2) and nb0) or (s(3) and b(0))) and a(0));
x <= not(h3 and h2 and h1 and h0);
y <= not((((((i0 and h1) or i1) and h2) or i2) and h3) or i3);
alu_13 <= not(cn and h3 and h2 and h1 and h0);
i3 <= not((s(1) and nb3) or (s(0) and b(3)) or a(3));
i2 <= not((s(1) and nb2) or (s(0) and b(2)) or a(2));
i1 <= not((s(1) and nb1) or (s(0) and b(1)) or a(1));
i0 <= not((s(1) and nb0) or (s(0) and b(0)) or a(0));
nm <= not m;
z0 <= not(cn and nm);
z1 <= not(((cn and h0) or i0) and nm);
z2 <= not(((cn and h0 and h1) or (i0 and h1) or i1) and nm);
z3 <= not(((((cn and h0) or i0) and (h1 and h2)) or ((i1 and h2) or i2)) and nm);
alu_45 <= not(f3 and f2 and f1 and f0);
f3 <= not((z3 and x3) or alu_55);
f2 <= not((z2 and x2) or alu_58);
f1 <= not((z1 and x1) or alu_61);
f0 <= not((z0 and x0) or alu_64);
x3 <= not((i3 and h3) or alu_66);
x2 <= not((i2 and h2) or alu_68);
x1 <= not((i1 and h1) or alu_70);
x0 <= not((i0 and h0) or alu_72);
alu_55 <= not(z3 or x3);
alu_58 <= not(z2 or x2);
alu_61 <= not(z1 or x1);
alu_64 <= not(z0 or x0);
alu_66 <= not(i3 or h3);
alu_68 <= not(i2 or h2);
alu_70 <= not(i1 or h1);
alu_72 <= not(i0 or h0);
nb3 <= not b(3);
nb2 <= not b(2);
nb1 <= not b(1);
nb0 <= not b(0);
-- fout <= f3 & f2 & f1 & f0;
-- c4 <= not(y and alu_13);
-- Xout <= x;
-- Yout <= y;
-- eq <= not alu_45;
fout <= transport f3 & f2 & f1 & f0 after 20ns;
c4 <= transport not(y and alu_13) after 30ns;
Xout <= transport x after 20ns;
Yout <= transport y after 20ns;
eq <= transport not alu_45 after 40ns;
end Structural;
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