Adjustable DC input for ADC reading

[permal]

Hi,

I'm attempting to design an analog input for a specific purpose.

The requirements are as follows:

• It can handle 0-48V.
• During normal operation the input voltage will be close to the the middle of the range span
• When deviating from the normal value, the input voltage will go either to ground or to rail voltage (disregarding any noise)
• Frequency of input change is less than 1Hz
• Protection against over voltage on the inside is needed

To accommodate this I've been thinking about a circuit like in the image. The potentiometer functions as a voltage divider and I can set it to a level where the current voltage range (0-5V, 0-12V, 0-24V or 0-48V) represents 0-3.3V on the output with protective clamping thanks to the zener diode. The 1M resistor represents the high impedance ADC.



Am I missing something that will prevent this from working in practice? The incoming voltage may have some noise (long cables in a house) so I need to add some lowpass/highpass filters too and I'd appreciate any hints on this.

Right know the output has a range of 0-3.3V, but it may be that I need to go down to 0-1V which makes the span much narrower which in turn will make it much more sensitive to noise. How should I handle such a case?

Is there a better way to scale 0-48V down two a voltage measurable by a uC? Can an Op Amp be configured to use negative gain (I tried but did't get it to work)?

Thanks!

PS:
For those wanting to try this circuit in a simulator, load this piece of text at http://www.falstad.com/circuit/

Code: [Select]

$ 1 0.000005 8.281975887399955 56 5 43
z 128 272 128 208 1 0.805904783 3.3
172 -128 128 -176 128 0 6 44.64 48 0 0 0.5 Voltage
g 128 288 128 336 0
w 128 288 128 272 0
r 48 160 128 160 0 1000
174 -80 128 -32 192 0 10000 0.9356000000000001 Resistance
w 128 160 128 208 0
w -128 128 -80 128 0
g -80 240 -80 256 0
w -80 240 -80 192 0
w 48 160 -32 160 0
r 160 160 208 160 0 1000000
w 128 160 160 160 0
O 208 160 240 160 0
x 147 246 196 249 4 24 3.3V
o 13 64 0 4098 5 0.1 0 1


[BrianHG]

Fixed resistors in place of your trim-pot will offer precision repeat-ability from circuit to circuit & without a trim-pot, you may get rid of the 1K.  It you want the adjustable range, keep everything as-is.

For filtering, since you are only worried about frequencies below 1Hz, adding a 1uf cap across the ADC input and GND will work fine.

Don't worry about noise, for this instance, resistors are pretty quiet.  Just make sire the GND sided resistor and 1uf cap is next to the aGND on your ADC.

[permal]

Awesome, thanks Brian!

[permal]

Oh - about the 1K resistor. I've but it there to prevent accidental short circuits so I'll be keeping that.

Now I just need to figure out a way to handle the 0-1V output case. Anyone with ideas?

[danadak]

Your 1M at input, generally not a good idea because of leakage, and
possibility of not getting the ADC sampling cap fully charged/discharged
to the next sample value. Look at tech manual and datasheet for leakage
value and ADC front end considerations. However all this being said you
might be able to get away with it because of the very low frequency/rate of
change at input.

One other on the 1M, it presents a high Z node subject to noise pickup
in the layout and environment design operated in.

If you leave 1M in and place a cap at ADC input of 1 uF, you have a time constant
of 1 sec. To charge to 1 lsb, 8 bits (assumed for UP) then it takes ~ 3 secs
to charge. At 12 bits it takes ~  8 sec.

http://www.analog.com/media/en/technical-documentation/application-notes/AN-1024.pdf


Regards, Dana.

[permal]

The 1M won't be part of the design, it is only representing the ADC in this schematic.

[Ian.M]

The zener doesn't turn on as sharply as you think it does and will cause non-linearity as you approach the upper end of the range.   You should use a precision clamping circuit that clamps to a voltage derived from the 3.3V supply rail (without dumping current into the rail. 

How many bits is your ADC and what value is its internal sampling cap?  With that information you can determine how much capacitance you  need at the ADC pin for the voltage not to shift more than 1/2 LSB during sampling.

[permal]

The zener doesn't turn on as sharply as you think it does and will cause non-linearity as you approach the upper end of the range.   You should use a precision clamping circuit that clamps to a voltage derived from the 3.3V supply rail (without dumping current into the rail. 

How many bits is your ADC and what value is its internal sampling cap?  With that information you can determine how much capacitance you  need at the ADC pin for the voltage not to shift more than 1/2 LSB during sampling.

Yeah, I know it doesn't cut off sharply, but as the input signal will only go to either rail or ground voltage when not being stable in the middle of the range that shouldn't e a problem. that said, if I can design it to be more multi-purpose that'd be a good thing.

So you're recommending something based on an Op Amp, like they show here? https://en.wikipedia.org/wiki/Clamper_(electronics)

The ADC has 12 bit, not sure of the internal sampling cap right now. If I knew it, how'd I go about calculating the capacitance not to shift?

[Ian.M]

We had a clamping discussion a few months ago:
https://www.eevblog.com/forum/beginners/overvoltage-protection-with-a-twist/

For less than 1/2 LSB shift:
   Cext > Csamp*2^(N+1)
where N is the number of ADC bits.

[permal]

Ah, thank you. 

[permal]

Well, after reading though the thread you linked, Ian.M, I realize that I know less about electronics than I thought  and I'm out on deep water. Thankfully I've only myself to answer to 

While I don't really need the inputs to be general purpose, i.e. I can probably go for my original design for my application, now that my curiosity has been piqued I'd really like to make them so. Both for the learning and the usefulness of such inputs.

I tried to make sense of the schematics in that linked thread but they're unfortunately too complicated for me at this stage so I'll have to start reading up on the different component and circuit types that were used.

Can I ask you to explain what "dumping current into the rail" actually means? As I understand it, the problem is that the voltage of the rail would fluctuate, possibly going above Vdd_max, but how? Does it have to do with charges in capacitors being released into the rail or something along those lines?

[Ian.M]

Most regulated supply rails are provided from either a linear regulator with a series pass element or a switching regulator with diode rectification.   Both are designed to supply current and neither has any provision to accept current from the load if the voltage rises above the setpoint.   As such, if your clamping circuit dumps current into the supply rail, the regulator output current will reduce to compensate.  However if it dumps more current into the rail than the loads on that rail are currently using, the regulator output currernt cant reverse to absorb the excess so the rail voltage will rise and bad things happen to voltage sensitive loads on that rail, usually resulting in critical loss of magic smoke.

[danadak]

In CMOS there are parasitic diode structures inherent in the technology
that can dump current into the supply rail if the diodes are forward biased.

Vin >= Vcc + Vdiode or Vin <= Vss - Vdiode will trun on these diodes.
Same for outputs

Vout >= Vcc + Vdiode or Vout <= Vss - Vdiode


See CMOS section of this http://www.ti.com/lit/an/sdya009c/sdya009c.pdf


Regards, Dana.