astable 555 duty cycle mystery

[oldguyjohn]

Hi everyone,  this is my first post on my first forum so let me introduce myself.  At the age of 69 I am attempting to learn some electronics as a hobby.  My level of maths is poor so please keep any answers logical and not too mathematical. The internet is a fantastic information resource but I have rapidly learned that some people giving advice or instruction don't have the required level of knowledge themselves to always be correct, but they can sound convincing. This can be a huge source of frustration to a beginner like me when trying to understand concepts. I am hoping a well founded forum like this will allow me to learn as the answers will no doubt be scrutinized and corrected if necessary by the large number of talented members.
As with most beginners I am playing with the 555.  I have an anomaly with the basic astable circuit so often published which is driving me crazy.  When I configure using separate feed and discharge resistors with diodes in both directions and using pin 7, I can get a 50% duty cycle.  When I configure using a single resistor from pin 3 to both charge and discharge I get approximately 33% low and 66% high.  Try as I might I can't understand this, as when I simulate the circuit I get 50%, but on the breadboard it's impossible without adding components.  As the resistance is the same in both directions, the voltage difference between Vcc and trigger and reset and ground appear the same I simply don't understand why the capacitor discharges faster than it charges?  I'm obviously missing something?  Can someone please explain?   Sorry if this sounds dumb but we all have to start learning somewhere.

[Andy Watson]

Can you post a photo of your breadboard?

[Ian.M]

CMOS '555' compatible chips will give pretty close to a symmetric 50% duty cycle with a single timing resistor driven from the output, but classic bipolar NE555 chips and bipolar clones wont, especially at low supply voltages because the output isn't rail to rail and has different saturation voltages for output high and output low.   

The other possible asymmetry is capacitor leakage - don't use electrolytics!

[oldguyjohn]

Thanks for the replies,
Andy - attached are photos of breadboard & scope traces
Supply 6V, resistor 3K9, all caps 1uF.

Ian - Your comments noted, first scope trace with NE555 and second trace using 7555 instead.
It's such a shame for beginners like me that so many other web contributors and text books state that a 50% duty cycle will always happen without explaining the differences between chips.  Hours of time spent thinking I was making an error when it appears the problem has been the shortcomings of the basic 555 chip.

Many thanks for your replies.
John

 

[oldguyjohn]

Sorry, can't master how to add more than one image? Oh got it now.

[Ian.M]

The other *nasty* issue with bipolar 555 chips is the output stage shootthrough as it transitions.  It will pull a current spike, typically hundreds of mA on each edge, and unless you have a beefy PSU, with good local decoupling, its likely to upset any other devices on the same supply rail.  The *ONLY* reason to use bipolar 555 chips is if you need more output current than the CMOS ones can handle in a totally Muntzed application with nothing else sensitive on the same supply rail - e.g. a simple timer relay with the 555 directly driving the relay coil.

[Zero999]

CMOS '555' compatible chips will give pretty close to a symmetric 50% duty cycle with a single timing resistor driven from the output, but classic bipolar NE555 chips and bipolar clones wont, especially at low supply voltages because the output isn't rail to rail and has different saturation voltages for output high and output low.   

The other possible asymmetry is capacitor leakage - don't use electrolytics!

Yes, and even the CMOS IC will not give a 50% duty cycle, if the output has a significant load attached to it.

[Ian.M]

Which is why it can be preferable to use the open drain Discharge pin + a pullup if required for the actual output if you've connected the timing resistor to OUT

[Zero999]

I prefer to use CMOS gates for this. The unused gates can be connected in parallel and used as a buffer.