Author Topic: Battery Backed SRAM Circuit - Logic Questions  (Read 666 times)

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Offline grantb5Topic starter

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Battery Backed SRAM Circuit - Logic Questions
« on: December 12, 2017, 07:25:17 pm »
Hi, I am doing a simple SRAM expansion on a legacy 8-bit micro circuit. The circuit now uses a socketed SRAM and there is a coin cell backup for it.

I am adding a small board that pops in the SRAM socket and bank switches a larger SRAM using physical SPST or SPDT switch(es).  My worry is current drain when system power is off and the coin cell is retaining the memory. The bank switching is done by raising or lowering the highest order address line(s).  When power is off I don't want to drain the coin cell because of bad circuit design.  Here is the basic idea, I hope it is clear:

Code: [Select]

                  .------U-------
 +5v---.   Vmem---| Vcc
       |          | 
       |          | 
       <          | 
       < 1k       |   SRAM
       <          | 
       |   SPDT   | 
         /--------| Axx (highest addr line)
       |          | 
       |          | 
       <          | 
       < 10k      | 
       <
       |
       |
      ===  GND
       =

 

Originally I thought tying the high side of the switch to Vmem that drives the SRAM.  On second thought, standard +5v seems smarter.  I don't want to "energize" that SRAM address line when 5vDC is off.  The resistor values are to-be-determined. I just don't want to draw more current than needed to attain the H and L logic levels.

"Vmem" is a diode combination of the coin cell and the +5vDC standard power supply voltage (whichever voltage is higher drives the SRAM).  Only the SRAM and a few gates are attached to Vmem. 

Or would it be better to tie it to some actual gate output?  I do have access to an unused 4011 gate that could be involved. This gate is powered by Vmem also.


« Last Edit: December 12, 2017, 07:36:39 pm by grantb5 »
 


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