Beginner needs your help solving biasing problem with an amplifier

[Evy]

Hello!

I have been trying to solve this excercise with a bias circuit for a negative feedback voltage amplifier for a week now. I think I need a helping hand. 


I have no clue how to solve a) for instance.

My knowledge:
I have previously studied the output stage transistor as a switch to approximate when clipping can occur in the output stage of the amplifier which is pnp transistor in this case. I have studied npn transistors and not pnps.

The image below comes from an excrecise I did previously where you can see a box (nullorn, ideal amplifier, two-port) and an output stage which is an npn transistor with a load R_L between the collector and emitter.

What I get from the problem:
The circuitry in the excercise is a tad more advanced. R₁ and R₂ are the feedback resistors. The two mirrored transistors make up a differential stage. R_C is biasing resistance (I have yet not figured out its purpose, I guess that it has something to do with the balancing of the differential amplifier's base voltages). R_L is the load and R_e is usedas a current source to deliver current to (from) the differential amplifier above. And I know that the pnp transistor has 2.5V on the emitter.

Goal:
I an now trying to somehow translate the cicuitry in the problem above to the simplified version (with that box above) with an pnp transistor wich I will later be able to analyze using the "swith model".

Can I get any helpful advice on how I can tackle this problem? Please go easy on me.

[Benta]

Well, for (a), the limit is set by the current sink of 1 mA.

As the peak output voltage is defined as 1.5 V, the load must be greater than 1.5/0.001, yielding 1.5 kohms.

This is not the load impedance, however, it is RL || (R1 + R2) = 1.5 kohms, so RLmin. is a bit higher (do that math yourself).
I'm ignoring the base current into the second transistor, as it should be negligible with the high betas listed.

[Evy]

Well, for (a), the limit is set by the current sink of 1 mA.

As the peak output voltage is defined as 1.5 V, the load must be greater than 1.5/0.001, yielding 1.5 kohms.

This is not the load impedance, however, it is RL || (R1 + R2) = 1.5 kohms, so RLmin. is a bit higher (do that math yourself).
I'm ignoring the base current into the second transistor, as it should be negligible with the high betas listed.

Thank you for your comment!

I have noticed that you calculate the load resistance as though the current 1mA is passing through the load but I do not understand why you do that. Could you please explain that part? Thanks in advance.

[Andy Watson]

I have noticed that you calculate the load resistance as though the current 1mA is passing through the load but I do not understand why you do that.

The original question asks for output without clipping - consider the mechanisms by which clipping will occur.

[Evy]

Clipping occurs when there is either too little or too much voltage across a transistor and if there is not enough current flowing through it. Transistor is in saturation or cut-off region of operation.

I don't understand how I should proceed from here.

[rstofer]

Assume that the output transistor is cut off and there is no collector current.  In this case, the only current that can flow through R1,R2 and RL is coming from the current source.  This sets one side of the maximum output current and, therefore, the minimum value of the load impedance.  At some point, I would expect the output transistor to source 2 mA max.  From this you can get the answer to b)

It's been a long time since I worked on this kind of thing.  I could be way off.

[Evy]

Assume that the output transistor is cut off and there is no collector current.  In this case, the only current that can flow through R1,R2 and RL is coming from the current source.

Perfect explanation!

This is the part where I get stuck:

This sets one side of the maximum output current

How? Should we assume that the base current into the differential amplifier is 0? Is the voltage at the base 0 too?

[rstofer]

There must be some condition of the differential amplifier that has no current through the left transistor and all the current through the right transistor.  I think...

So, that is the condition under which the output transistor is cut off.  The base is pulled to Vcc by Rc and there is no collector current.  Only the current source is driving the load.

The other condition is where the output transistor provides 2 mA and if B=100, the base current would be on the order of 20 uA.  This should be the situation where the first stage is required to deliver the maximum current.  Again, I'm just guessing...

[Benta]

Assume that the output transistor is cut off and there is no collector current.  In this case, the only current that can flow through R1,R2 and RL is coming from the current source.

Perfect explanation!

This is the part where I get stuck:

This sets one side of the maximum output current

How? Should we assume that the base current into the differential amplifier is 0? Is the voltage at the base 0 too?

Well, look at it this way:
The current sink will always draw 1 mA (provided it's within its specified operating region).

If the output transistor is cut off, only the current sink will supply current to the load. The effective load seen by the current sink is (R_L || (R1 + R2).
To be able to provide an output peak voltage of -1.5 V at this point (which is the clipping point, as the output transistor is off), the minimum R_L is thus defined.

Now looking at the positive swing where the output transistor is active, and R_L has the minimum calculated above, the transistor has to supply 2 mA.
Why? Because of symmetry. It has to source 1 mA to the current sink, and 1 mA to the effective load R_L || (R1 + R2).

From here you can calculate the maximum needed base current into the output transistor, which will be 20 uA at a beta of 100.

[rstofer]

The other condition is where the output transistor provides 2 mA and if B=100, the base current would be on the order of 20 uA.  This should be the situation where the first stage is required to deliver sink the maximum current.  Again, I'm just guessing...

The first stage doesn't so much 'deliver' current as 'sink it'.  Poor choice of words on my part.

[Benta]

The first stage doesn't so much 'deliver' current as 'sink it'.  Poor choice of words on my part.

Don't worry about it, I fall into the same trap. The problem is the choice of the words source and sink.

To be consistent, it would be better to work with the terms "voltage source" or "current source" only, and use + or - to indicate polarity/direction. It works when describing voltage, but often not with current.

[Evy]

Thank you for all of your replies. I have calculated the resistance which i got to 1736.84 and it was correct! Yey, hehe   


How do I proceed with b)? The key in the book mentions that I should calculate it with the help with the collector current since B_f * i_b = i_c but I don't have the value for the collector current... 

Is there something that I should assume again?

[xavier60]

For 1ma of collector current, the base current needs to be 10ua. I think that 10ua should also flow through Rc. Assuming that B-E voltage is 0.6v, Rc will be 60K.

Edit: On second thoughts, if Rc is made open, then current through the differential transistors could be set to 10ua each.

[Evy]

Why is the collector current 1mA? I know that the current source of 1mA, or as some people call it "current sink", is directly below it. But, there are other branches (branch 1: with R₁ and R₂, branch 2: R_L) where current can flow,  connected to the collector. As far as I am concerned, the only plausible explanation I can think of to get the 1 mA current to flow from collector and directly "into" the current sink is to assume that there is no current flowing through branch 1 and branch 2. Is that what you assume?

[xavier60]

As with most amplifiers that are powered from split rails, the output is expected to be zero volts DC. It is best to assume that no signal is applied to the input for now, just zero volts.
While there is zero volts at the output, no current flows through the 2 branches. 

[Evy]

What are split rails? Is it the 2 DC sources that power V_CC and V_EE with a reference ground in between?

[rstofer]

What are split rails? Is it the 2 DC sources that power V_CC and V_EE with a reference ground in between?

Yes

[Evy]

Oh okay, so I should assume that there is no amplification just yet  ->  the input signal V_S is 0  ->  the output signal V_L is zero  ->  the current in the branch with R_L is zero  AND  current in branch with R₁ and R₂ 0  ->  current in the collector = current of the current sink


I think I got stuck where the color is red. Why is the current in the branch with R₁ and R₂ 0 now? Is it because there is no amplification and therefore no feedback through them since this is a negative feedback amplifier?

[xavier60]

There is a negative feedback path through the R2/R1 divider to the RH differential transistor.  The differential transistor pair amplify any voltage difference between their bases and vary the drive current to the output transistor in a direction that corrects any tendency of output voltage change.
The output voltage won't exactly be zero volts until ideal values of Rc and IE are found which I'm a bit puzzled about. Usually differential amplifier circuits are designed for the 2 transistors to pass the same currents at idle state.

[Benta]

I think I got stuck where the color is red. Why is the current in the branch with R1 and R2 0 now?

You can look at it in two ways:

1: input voltage is zero, so the base voltage of both differential transistors is zero, as the emitters are connected and they have the same V_BE.

2: in an earlier analysis, we agreed that the base current into the right input transistor is negligible, so it will not influence the current through R₁ and R₂.

Also forget "xavier60"s guess about 10 uA through R_C, it's way off. We've already determined that 20 uA base current for the output transistor is needed.

[Evy]

I think that I am very close the solution to this problem now. Thank you very much to all of you for your help to this point!!!

I calculated the current in b) to 10 uA or should I have the double for some reason?

[Benta]

b) cannot be answered, as it is phrased imprecisely. What exactly is meant by "minimum current in the input stage"? Current through R_C or R_E?

[Evy]

b) cannot be answered, as it is phrased imprecisely. What exactly is meant by "minimum current in the input stage"? Current through R_C or R_E?

It's most likely the current through R_E.

[xavier60]

I think Rc is supposed to be infinity. Any other value doesn't allow zero to 20 uA base current drive range for the output transistor and symmetrical current through the differential transistors of 10 uA  each while the amplifier is idle.
 
Extra:
For any value of Rc other than infinity, it is possible to choose values for IE that give only one of these conditions,
1: zero to 20 uA base current drive range or
2: symmetrical current through the differential transistors,
 not both conditions at the same time.

[xavier60]

Evy, What answers did you submit?