Author Topic: Best practices in multiple CPU/FPGA PCBs - power design  (Read 1036 times)

0 Members and 1 Guest are viewing this topic.

Offline CptRamblerTopic starter

  • Newbie
  • Posts: 1
  • Country: sk
Best practices in multiple CPU/FPGA PCBs - power design
« on: February 23, 2017, 09:27:22 pm »
Hello. I'd like to ask a little question :). I've done design for some "small" boards mainly consists of one CPU (soc), MCU or FPGA. Power design for them was quite simple a straight. Now I'm working on a board, which have FPGA (spartan-6) and Freescale/NXP iMX6 SoC on the same PCB. I've never done power design for two chips on one PCB. I'd like to ask what are the best practices/steps in power rail and power design at all in that complex projects. For example. Power sequencing. How is it possible to manage that with multiple different CPUs/FPGAs, etc. Btw, I don't want anyone to design it for me of course :). Maybe it's a dumb question :).

Thanks.
« Last Edit: February 23, 2017, 09:34:08 pm by CptRambler »
 

Offline james_s

  • Super Contributor
  • ***
  • Posts: 21611
  • Country: us
Re: Best practices in multiple CPU/FPGA PCBs - power design
« Reply #1 on: February 23, 2017, 09:50:30 pm »
Take a look at some existing commercial products and see how it's done. For what you're doing I don't think you'll need power sequencing, just lots of strategically placed decoupling capacitors. If you're using a multilayer board you could have power and ground planes and then local regulators near the main ICs to get whatever other voltages they require.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf