Bidirectional TVS a better choice?

[HackedFridgeMagnet]

Have you tried using a design simulator such as LTSpice?
It's quite useful, doesn't take long to learn.

[Boltar]

I do have it installed, but I find SPICE to be a very frustrating simulator, it's always stopping with errors, especially at high frequencies, convergence and GMIN and what not. I'll give it another shot though.
Scroll wheel is back to front for zooming, there doesn't seem to be any obvious way to shift your viewpoint, i can't seem to delete just a part of a wire, it deletes the entire net including all components on it. . There also doesn't appear to be any way to search the component database. Sorry, but I really don't like it. I'm having enormous problems trying to figure out how to invert the comparator output in LTSpice. The gate driver I use is essentially a level shifting not gate,. 0V in=12v out and 5v in=0v out, and in LTSpice I'm lost, i'll have to use another comparator to emulate it

EDIT: Sorry no, I really cannot get on with this. I've tried a few simulators and they all have their quirks, but I manage fine with most of them, but this one, it really is dreadful.

[Boltar]

How about this one? I've put no current limiting in yet, I'm getting to that (do 1 thing at a time), but I think this method eliminates the need for the oscillator.


To start, there will be no voltage at vout (the LOAD) so comparator IC2's output will go to the +ve rail, this will then start to charge C1 through R2 until the voltage across C1 reaches 3V, then comparator IC1's output will go from high to low, turning the mosfet on, this causes vout to rise until it goes over VREF, at which point IC2's output will go low, allowing C1 to rapidly discharge through D1 and bring IC1's output (almost) instantly high again turning the mosfet off. Essentially, C1, R2 and D1 introduce an unavoidable delay between IC2 going high and the mosfet actually turning on, however there is virtually no delay when it needs to be turned off.  How viable is this idea?

EDIT: I could wire the current limiting comparator through a shunt on the source of Q1, and set it to go LOW output when the current is too high, then wire the output via a diode to C1 causing the cap to discharge if the current gets too high, making the circuit hiccup, as the frequency still cannot go above the charge rate of C1.?

I'm a little worried about the frequency. The higher I can get it, the more effective the output stage will be, but if I have my maths correct. To achieve a 100kHz square wave, i'd need 10ns from phase to phase, now, if the duty cycle needs to be quite short, that switch on and off time will be way into the ps range in order to avoid huge ramps and ohmic states in the mosfet. How do I avoid that, there's not many comparators in the ps speed range.

[T3sl4co1l]

Right, I think I'm following you, in short terms I need an oscillator with a relatively short duty cycle and follow this logic?

Gate To Be Turned Off when VOUT is greater than VREF+Hysteresis -OR- Current Sense is greater than Current Limit
Gate to Be On when VOUT is less than VREF-Hysteresis -AND- Oscillator Pulse is High -AND- Current Sense is less than Current Limit
Thus I need a flip-flop as you described to prevent the gate turning off when the oscillator pulse is low, the oacillator should only be used for the logic of turning it on, not turning it off.

It should be reset dominant, so "if CS > CL, gate off" takes priority.  Also, CL should be controlled by an error amp (which can be an op-amp with compensation, or if you must... ADC --> PID register --> DAC).  But that's more or less the right idea.

They give the logic diagram of course, so if you don't mind reading RTL,
http://www.ti.com/lit/ds/symlink/uc3843.pdf

I also think I know what you mean about the source being grounded, that's how I always picture P devices, I imagine them like an N device but with their view of the world inverted, they see the +ve rail as ground and the -ve rail as a negative supply voltage.

Good, that's exactly what's going on.

Unfortunately, due to the established system in place for these kind of devices, the eventual load is always common to the supply negative (the load is put into the mouth using a metallic mouth piece which is electrically common to -ve due to the power supply also being mains earthed to the -ve to prevent a psu failure from electrocuting someone's face) so using N channels is not impossible, but far more tricky.

I'd be more comfortable with 8kV medical isolation... or better yet, a plastic appliance.

Not sure if there's regs specific to oral appliances.  Sounds medical-ish though.  Yeah, grounded is better than not, but not ideal...

EDIT:
To help me visualize logic, I often try to write them as computer code, obviously this would be impractical without a 100mHz processor and fast ADC,

Well, it wouldn't be terrible with a >10MSa ADC and an FPGA.  But it's so vanishingly little logic that it's of course pointless (it synthesizes to a single R-S flip-flop, maybe with some AND/OR/NOT stuff to resolve the specific conditions).  Implementing it in software would be...grotesque...

Another problem is I somehow have to detect the load resistance. I currently do this by applying 5V to the load through a 220 ohm resistor and an npn transistor (to prevent the actual vout getting back into the resistance sensing circuit) and then using an opamp to amplify the node between the two. This circuit is switched on and off by the MCU as it doesn't need to be constantly sensing it, only once every 3 seconds or so and then it's only on for a few milliseconds. Now this becomes more complex, the vout has a cap between it and ground, so this approach won't work,

Nice thing about building a current-mode circuit is: if you tell it to deliver no current, it'll happily just sit there, off...not delivering any current!  You can manipulate the current limit or voltage reference signals at will (say, by summing an error signal from a DAC, or analog switches to gate in something else), so you don't need to diddle around with junk like that -- it all stays nice and neat and in the same loop.

Given the cap, you will of course want to pulse it for on the order of a millisecond, then leave it off until the next test.  The current doesn't need to be much (you may even have trouble adjusting it low enough), but whatever you get is fine, as long as you know what it is, and it's not dangerous or anything (an open circuit load still takes time to charge the cap, and you can probably detect that easily enough with a well-timed ADC sample).

Argh, the problems are too big. I have no idea how these other manufacturers manage to produce a board that can do everything I want and make it so small. There's a board out called an SX350, it can output 50W to a load of as low as 0.2 ohms and it measures less than 30mm square. It can sense resistance, it has ground common load, current limiting. Hell, just the size of the shunt resistor alone to handle shunting to a 0.2 ohm load would be crazy, not to mention the amount of power I'd lose through it. *sigh*

That sounds quite reasonable.  If size were absolutely important, I could probably do better.  But there's nothing unreasonable about a PCB that size, assuming you can get the heat out of course.  It just seems overwhelming because you have all these jagged, disparate pieces in your mind, still coming together.

Tim

[Boltar]

Tim, if I could afford to I'd send you a bunch of money. You've been super helpful and patient explaining all this to me and you explain things in an entertaining way too. Seriously, thank you for taking the time to go into so much detail. Top geezer. A big thanks to all the others who posted too.