Well, you do it piece by piece, of course!
Signals move at finite rates. (They also have all continuous derivatives, but we can cheat and use just one continuous derivative.) So, initially, drain voltage is 10V, and gate voltage is 0. Now a step comes along and gate voltage starts rising. Actually, gate current starts rising, and voltage begins to swing -- the gate capacitances charge, which includes Cgd, which is important, because when Vgs passes Vgs(th), Vds starts falling, and Cgd has to charge by Vgs(final) + Vdd, not just Vgs. This occurs during the linear range, when drain current is rising and drain voltage is falling.
You can calculate how long the turn-on event takes. If your gate driver is an ideal Thevenin equivalent, with a perfect speed driver, some total series resistance (usually the driver resistance, plus a small external resistor, plus the MOSFET's internal gate spreading resistance), and the gate charges like a capacitor, then the 0-63% rise time is t=RC. The 10-90% will be more like 2RC. The gate doesn't charge like a capacitor, because it's all kinds of nonlinear, but as long as you don't care too deeply about the exact waveform (it won't be an exponential ramp), the time will be representative. Oh, and what to use for C? Certainly not the figure they give at Vds = Vgs = 0V or whatever. No, you want the charge equivalent. So look at Qg(tot) / Vgs(on). Maybe it's 48nC at 10V, so call it 4.8nF for the average/effective capacitance.
Actual rise/fall time at the drain will be shorter, because most of the voltage change occurs during the Miller plateau when Cgd is charging.
Now that you know turn-on time (roughly), you can calculate turn-on energy.
Switching on into an empty inductor DCM (discontinuous) or BCM (boundary conduction mode), current stays low during turn-on, so the energy dissipated is essentially Cgd + Cds. You can guess the equivalent energy (E = 0.5 * C * Vds(off)^2), or it's occasionally specified in the datasheet (equivalent capacitance, energy related; or drain charge / energy versus voltage).
While the transistor is on, current rises approximately linearly with time (assumes Vds stays low and Vdd stays constant). The conduction power dissipation is then a rising parabola, because P = I^2 * R and I = t * Vdd / L. Recalling calculus, the area of a triangle is (1/2) * w * h; the area of a parabolic section is simply 1/3 instead. So, the conduction power is (1/3) * D * Rds(on) * Ipk^2 (for duty cycle = D).
When the transistor turns off, first the gate voltage falls a bit, then drain voltage starts rising. Drain current remains near Ipk. Cgd is charging (in the reverse) here, and you get another Miller plateau. Once drain voltage gets clamped by the diode, drain current finally falls (the diode grabs all the inductor current) and the transistor turns off. During this transient, drain voltage rises roughly linearly (not actually, because again, capacitance isn't linear), while drain current remains constant. In the second phase, drain voltage remains constant while drain current falls. So, power loss is a triangle of height Vout * Ipk and width t_off, or a turn-off energy of (1/2) * Vout * Ipk * t_off.
While the transistor is off, leakage can safely be ignored. If you have two transistors in an inverter (instead of one plus a diode), you can get hard switching when the opposite transistor turns on. The fast dV/dt gets coupled by Cgd into the gate, which can cause it to turn on momentarily (needless to say, the losses can be huge, because the inverter is momentarily shorting itself out). This isn't a common problem with MOSFETs, but it can be with IGBTs. The easiest solution is some negative bias in the 'off' state (usually +15/-5V drive, instead of +10/0 or whatever).
So, add up all the power losses, and for the energies, multiply by switching frequency to get their contribution to power. Sum it all up and that's your switch loss.
If you're operating in CCM (continuous current mode), the inductor current will be nonzero by the time the transistor switches on again. The diode will still be conducting, so the transistor is going to yank it off in hard switching. There are a couple of things to keep in mind during this transient, such as loop inductance (between transistor, diode and load capacitor), gate voltage dV/dt (the transistor has transconductance, which sets dI/dt, which controls diode recovery speed and peak current). In any case, the result is much the same as during turn-off, except that Ipk is I_L(min) plus diode recovery current. If you're using a schottky diode, you don't have to worry about reverse recovery, but the junction capacitance is much higher, which can cause problems all its own (it still looks like reverse recovery, though not with the extra delay time in there).
Overall system losses also include the diode (you can assume it has a constant Vf, so the power is 0.5 * Ipk * Vf * (1-D) at duty cycle D), inductor (conduction losses and, if possible, eddy current and core losses -- an inductor specified for DC only, will probably run 10-100% hotter under switching conditions!), capacitors (ESR -- calculate like transistor conduction losses, but for the other half of the waveform) and anything else nearby (current sense resistors, damper / snubber components, maybe a fraction of a watt for the control circuitry, etc.).
If you have a good simulation (your example is obviously not a good realistic one
), you can also measure the loss in various components. But do make sure it's a very precise simulation (lower RELTOL and other TOLs, smaller maximum timestep, higher order integration methods) because SPICE is generally very bad at calculating rapidly changing parameters, and getting the sums and differences correct over time (very broadly, if you calculate Pin, Pout, and all the losses inbetween, Pin = Pout + Ploss will only be true within a factor of RELTOL, or probably much worse).
Tim
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