One of the "Electronic Design, Art, Science and Personalities" books has a lot of information on the original P1 op-amp design. It won't tell you how to design a CMOS op-amp in HSpice, but it will help put the foundations in place, and as the mask set for the CMOS will be about $100,000 then I suspect it's worthwhile sorting out the foundations.
thank you for your recommendation. :)But now I am reading Allen's book. In fact all I want to do is just design an op amp using IBM 0.13-micron CMOS fabrication process. And this op amp must be meet some specifications. I can only get transisitor model now, not the .lib for Hspice or Cadence. How can I do about it?
you are either trolling ,wasting our time or wasting your time.
you talk about ibm 130 nanometer process but clearly have no clue about how to design silicon.
first of all you will need
- the schematic editor ( most likely Cadence Opus) so you can draw up the schematic of the opamp.
- the p-cell generators for the transistors. so you know their width, length and doping
- Dracula , LVS and the extractors. so you can verify layout versus schematic , design rule checking and extract the netlist with electrical properties and parasitics.
- Access to an IC simulator like Eldo to run the extracted model
anything else doesn't fly...
If you have the transistor models you can try to create spice elements and do a rudimentary sim. but that will not yield a correctly working opamp.
ultimately you will need to extract form the placed layout and run that one, and then you will need access to the above tools. there is no way around it. That is how silicon design works.
Home
Help
Search
Login
Register
