Author Topic: CD4093 Nand Gate  (Read 8219 times)

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Offline 0x007Topic starter

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CD4093 Nand Gate
« on: May 30, 2015, 02:59:24 pm »
Hello every one ,
I am reading the data sheet of the 4093 nand gate and I can't understand the currents the chip can output.
According to the data sheet the high level current at 5v will be -0.88 mA ,and at the low level will be 0.88.
why is it inverted , shouldn't it be positive at the high level and negative at the low ?
and why it is negative at all?
Other thing that bothers me is why it is so low ?, according to the data sheet it's a bufferd ic "Standard B-series output drive", so shouldn't the current be higher ? 

The data sheet : https://www.fairchildsemi.com/datasheets/CD/CD4093BC.pdf
 

Offline fubar.gr

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Re: CD4093 Nand Gate
« Reply #1 on: May 30, 2015, 04:57:01 pm »
I guess the positive/negative numbers are because the IC is sourcing/sinking current respectively.

No idea why current is negative when the output is high though.

Offline Zero999

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Re: CD4093 Nand Gate
« Reply #2 on: May 30, 2015, 05:41:49 pm »
Whether the current is positive or negative depends on the point of reference. If the output pin is taken as the reference then any current flowing out of it (assuming conventional current flow) will be negative.
 

Online T3sl4co1l

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Re: CD4093 Nand Gate
« Reply #3 on: May 30, 2015, 05:54:48 pm »
You can roughly assume that the output pin characteristic resembles:

A Thevenin voltage source, where
- The voltage is either VCC or VSS
- The series resistance depends on supply voltage, typically around 500 ohms at 5V, down to about 250 ohms at 15V
- The series resistance is higher in the output-high state, and lower in the output-low state, by about 20% each (so at 15V, it acts like an average 250 ohms, but it's more like 200 ohms down and 300 ohms up)
- Pin protection / body diodes go from VSS to pin to VDD, with lower series resistance (10s of ohms?)

Input pins can be modeled the same way, but without active drive (obviously), dominant capacitance, and a softer diode clamp behavior.

The guaranteed limits they put on performance are used to fix hard points in the V-I range that they must meet.  If you look at the average slope of those points (i.e., how much voltage drop occurs at +/- 0.88mA load), you should see something near the Rds(on) figure.  Typical parts will do much better.

As for sign, datasheets usually define that positive current is entering the pin, and negative is leaving.  It should say somewhere.  (In a logic family, such definitions may not be in every individual datasheet, but in a common family reference paper or application note.)  You can just as well figure "well, it's the output-low state, so it must be a sinking current, regardless of what sign they wrote on it", and vice versa.

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Offline 0x007Topic starter

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Re: CD4093 Nand Gate
« Reply #4 on: May 30, 2015, 07:12:04 pm »
Ok, now I have some sort of understanding.
but if the maximum current it can drive is 0.88mA , its will probably not be able to drive a darlington pair or will it ?
I don't even know if it worth the effort I am putting in to it, I need an oscillator to generate a carrier frequency ,does the duty cycle matter if the frequency is consistent ?
I will probably use a 555 timer instead.
 

Offline c4757p

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Re: CD4093 Nand Gate
« Reply #5 on: May 30, 2015, 07:20:53 pm »
Nah, you're misunderstanding the currents.



It specifies a high-level output current of 880µA at an output voltage 0.4V below VDD. In other words, an output impedance of 0.4V/0.88mA = 455 ohms.
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Offline 0x007Topic starter

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Re: CD4093 Nand Gate
« Reply #6 on: May 31, 2015, 06:31:15 am »
I don't understand so how much current it can drive then ?
if you say it has impedance of 455 ohms at 4.6v its ~10 mA ?
what I learned in school is look at what the data sheet say and don't try to interpret it in different ways .
 

Offline PSR B1257

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Re: CD4093 Nand Gate
« Reply #7 on: May 31, 2015, 06:51:57 am »
Quote
I don't understand so how much current it can drive then ?
As the datasheet says, less then 1mA at VDD=5V.

Quote
if you say it has impedance of 455 ohms at 4.6v its ~10 mA ?
No, thats the (theoretical) short circuit current, at least almost. If you calculate the short circuit current, you take the open circuit voltage of the source.

Quote
what I learned in school is look at what the data sheet say and don't try to interpret it in different ways .
The good thing about physics is, that there is not much to interpret .
In theory, there is no difference between theory and practice. But, in practice, there is.
 

Offline Zero999

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Re: CD4093 Nand Gate
« Reply #8 on: May 31, 2015, 10:32:06 am »
but if the maximum current it can drive is 0.88mA , its will probably not be able to drive a darlington pair or will it ?
What's the collector load?

The main thing to watch out for is that the power dissipation rating of the IC is not exceeded. At 5V the CD4093 can stand a continuous short circuit on one of its outputs so you could drive a transistor with no base resistor, as long as you accept the output will be clipped to the base voltage (about 0.7V) so won't give a valid logic level.
 

Offline SeanB

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Re: CD4093 Nand Gate
« Reply #9 on: May 31, 2015, 10:39:42 am »
Most darlingtons have a gain over 1000 so even with under 1mA base drive you will easily be able to handle a 5A load. If you want more current forget the darlington and use a logic level MOSFET instead, lower on state power dissipation from the sub ohm on resistance, as opposed to the darlington which will always have 1V2 to 2V drop across when fully on, irrespective of the current.
 

Offline onlooker

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Re: CD4093 Nand Gate
« Reply #10 on: May 31, 2015, 12:14:43 pm »
I think the key point for beginners is that this is CMOS. The output is basically two FETs in series. One may 1st think the equivalent circuit as a resistor voltage "divider" with one of the resistors being about 100 to 400R and the other being infinite (open). Which one is the low value resistor depends on the on/off output state.

Since one leg is open, one can now view the equivalent circuit  as a single ~400R resistor  connecting the output node to either Vss or Vdd depending on the on/off state. The sign of the current is just the consequence of the two different Vss/Vdd connections.

It would be more intuitive if, instead of, currents IoL and Ioh, let the reader think in terms of resistor and use ohm values. In fact, this is what is done in their doc about standard B-series output drive.

With this single resistor view, it should be easy to understand
1). what would be the max output current when the output is short to Vss or Vdd.
2). When shorting the output, is the power dissipation in spec.
3). What is the max drive  current available when the output logic state needs to be maintained.


« Last Edit: May 31, 2015, 12:45:50 pm by onlooker »
 

Offline 0x007Topic starter

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Re: CD4093 Nand Gate
« Reply #11 on: May 31, 2015, 04:20:23 pm »
So basically I need to refer to current in a CMOS data sheet as the current on a "resistor" in side the chip when there is no load, and from that I can tell the drive current ?
 

Online T3sl4co1l

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Re: CD4093 Nand Gate
« Reply #12 on: May 31, 2015, 04:20:42 pm »
I don't understand so how much current it can drive then ?
if you say it has impedance of 455 ohms at 4.6v its ~10 mA ?
what I learned in school is look at what the data sheet say and don't try to interpret it in different ways .

"Datasheet says" works fine when you're at or below the numbers.  Example, if you were asking about < 0.88mA, you can be guaranteed to have 0 to 0.4V or 4.6 to 5.0V as output levels.

When you're asking about more, you have to make assumptions about the physics of the device.  If they provide a typical output V-I curve, you can use that to infer what happens at other voltages.  You aren't guaranteed to have those curves met (the guaranteed data is only a single point on the graph), and in principle, the curve could be anywhere else on the graph, as long as it meets the limit in that small range where the data says it has to be.

Note that you may have to view the logic family datasheet to find these curves.

In reality, there is absolutely no physically possible reason for a simple output stage to exhibit anything more complicated than the curve given.  The variable that they're protecting against is a matter of slope and scale; some devices will roll off sooner than others, some will be steeper or shallower than others (higher or lower resistance in the Rds(on) region).

Although CMOS outputs do flatten out at large voltage drops (tending towards a constant current characteristic), it's not usually much, and you can guess the short circuit current Isc = Vdd / Rds(on) is a good guess.  It might be as much as double the actual value, but this is well into the extrapolated range, so that shouldn't be unexpected.

The most important consequence is this: you aren't going to get more power output, or drive capability, than Vdd^2 / Rds(on) suggests.  And more likely, a quarter of that, because of the  power matching theorem (i.e., Rsrc = Rload, which isn't a terrible approximation for the known output V-I curves here).

So if that's not enough drive power for your load, you'll need something better.

Have you considered a MOSFET?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline Zero999

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Re: CD4093 Nand Gate
« Reply #13 on: May 31, 2015, 05:45:10 pm »
So basically I need to refer to current in a CMOS data sheet as the current on a "resistor" in side the chip when there is no load, and from that I can tell the drive current ?
Why not post the full schematic?
 


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