Author Topic: Chip making process  (Read 26930 times)

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Offline amyk

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Re: Chip making process
« Reply #25 on: October 15, 2018, 11:29:18 am »
1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.
See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.
 

Offline mikeselectricstuff

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Re: Chip making process
« Reply #26 on: October 15, 2018, 12:17:12 pm »
1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.
See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.
Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2
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Offline coppice

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Re: Chip making process
« Reply #27 on: October 15, 2018, 03:07:27 pm »
1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.
See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.
Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2
Since those devices run at 5V, and presumably do not regulate inside the chip, they are probably on a 500nm or 800nm process. That does push the size up quite a lot, even for such a simple chip.
 

Offline mikeselectricstuff

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Re: Chip making process
« Reply #28 on: October 15, 2018, 03:25:04 pm »
I'm pretty sure the 10F322 uses a lower core voltage internally - there is an internal regulator "which provides operation above 3.6v" according to the datasheet
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Offline coppice

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Re: Chip making process
« Reply #29 on: October 15, 2018, 03:28:55 pm »
I'm pretty sure the 10F322 uses a lower core voltage internally - there is an internal regulator "which provides operation above 3.6v" according to the datasheet
I missed that. If they are regulating to run the core at a maximum of 3.6V its probably a 350nm process.
 

Offline jmelson

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Re: Chip making process
« Reply #30 on: October 15, 2018, 03:36:07 pm »
I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Yes, certainly, transistors are the basic element.  But, actually, there is a lower level, which is the individual layer masks.
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Will the same be applicable for digital circuits?
Yes, at the lowest level, it is all analog, and all transistors, resistors and wires.
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2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
Yes, you must select a process first, to have the parameters of the silicon, doping, etc. before you can start describing the transistor channel width and length.
Each transistor is described by length, width and type (doping).  Each process has a "design kit' which has all these specs.
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3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
You really CAN'T!  These are proprietary parts, and TI, etc. will not give out the internal design.  So, you have to redesign these parts in the process you select.
Then, simulate until the performance is what you want.
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4. What tools are required for creating and sending the designs to mask maker and foundry?
There are several major programs.  If you are not at a university, the commercial design suites are very expensive, like 50K US dollars/seat, with massive costs to renew each year.   Cadence is the leader, Mentor is still used, I think.   There are also some open-source design packages.
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5. What are the costs and MOQ involved in the whole process?
I am involved in a university project making chips for nuclear physics experiments.  We use MOSIS, and a university Cadence license.  We used to use the AMI (now ON Semi) C5 process, a 350 nm 5V process.  We just did our first chip with the Austria Semi (AMS) fab.  Their design kit is WAY better than the AMI/ON Semi kit.  Minimum order is 40 parts (untested) and you can order more in 40-part increments.  Our chip was fairly large, about 5 x 7 mm, and the cost for 40 parts would run some $28K US dollars, unpackaged.  They usually charge something like $7500 for packaging.
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6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?
Well, MOSIS combines dozens of masks from different projects onto one wafer, and thus spreads the cost of the masks across multiple projects.
So, you must provide them the mask layers, generally as a "Calma stream", and they have to meet a number of criteria to be acceptable for fabrication.
If the mask data is accepted, then MOSIS handles the whole interaction with the fab.

Jon
 
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Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #31 on: October 15, 2018, 04:02:06 pm »
We use MOSIS, and a university Cadence license.  We used to use the AMI (now ON Semi) C5 process, a 350 nm 5V process.  We just did our first chip with the Austria Semi (AMS) fab.  Their design kit is WAY better than the AMI/ON Semi kit.  Minimum order is 40 parts (untested) and you can order more in 40-part increments.  Our chip was fairly large, about 5 x 7 mm, and the cost for 40 parts would run some $28K US dollars, unpackaged.  They usually charge something like $7500 for packaging.
How much time does Mosis take to send you back the chips, once you send them the design files?
How do you handle the unpackaged chips, do they need special care? do you need to pour epoxy on them before testing them? Do they come with pads to solder on the PCB?
How does the software help you in designing the circuit, does it have high level components like op-amps, adc's etc. and them during synthesis these blocks get flattened to transistors?
 

Offline jmelson

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Re: Chip making process
« Reply #32 on: October 15, 2018, 04:54:08 pm »

How much time does Mosis take to send you back the chips, once you send them the design files?
How do you handle the unpackaged chips, do they need special care? do you need to pour epoxy on them before testing them? Do they come with pads to solder on the PCB?
How does the software help you in designing the circuit, does it have high level components like op-amps, adc's etc. and them during synthesis these blocks get flattened to transistors?
It takes at least 3 months to get the chips back.  Since we require some different packaging (completely filled plastic packages) that costs a few extra weeks.
We do not get unpackaged chips, we always get them packaged.

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon
 
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Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #33 on: October 15, 2018, 05:24:29 pm »

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon
Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?
 

Offline coppice

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Re: Chip making process
« Reply #34 on: October 15, 2018, 05:28:54 pm »

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon
Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?
Unless you can find a canned analogue solution that exactly suits your needs, licensable in a reasonable manner, tailored for the exact process you will use, expect your analogue development to be fairly expensive and protracted.
 

Offline Richard Crowley

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Re: Chip making process
« Reply #35 on: October 15, 2018, 05:34:45 pm »
Do these design kits need to be purchased from the foundry? eg. AMS
The performance (threshold voltage, speed, current capacity, etc.) of each transistor is inextricably tied to the process parameters.  So, unless you can get something tied to the selected process, you would likely be designing from a lower level.

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Its interesting to hear that each transistor in an analog circuit needs to be manually crafted.
Because a transistor of exactly the same dimensions will operate quite differently depending on what process it is made with.  And, of course that applies to ALL circuits.  There are no "digital circuits".

Quote
Your would need a quite a big team to make a large circuit wouldn't it?
Define: "large circuit"?  Do you mean 1000s of transistors or billions of transistors?
 
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Offline Wimberleytech

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Re: Chip making process
« Reply #36 on: October 15, 2018, 06:14:36 pm »

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon
Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?
Unless you can find a canned analogue solution that exactly suits your needs, licensable in a reasonable manner, tailored for the exact process you will use, expect your analogue development to be fairly expensive and protracted.

Just now read through this thread.  Lots of good information and answers.

Lemme make it easy on you.  I will design your chip for you.  Send me the spec (just sketch it on a bar napkin if that is convenient) and I will get started.  Paypal is fine for billing (how well funded is your Paypal account?).
 :-DD
 

Offline srce

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Re: Chip making process
« Reply #37 on: October 15, 2018, 06:43:53 pm »
Do these design kits need to be purchased from the foundry? eg. AMS
The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.
 
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Offline jmelson

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Re: Chip making process
« Reply #38 on: October 15, 2018, 06:58:23 pm »

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon
Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
In general, you have to supply an NDA to MOSIS, they get it approved through the foundry and then you get the design kit, for no extra fee.  I guess that is all rolled into the price at MOSIS.
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Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?
Well, no.  We have a professor of IC design, he has masters students, and guides them through the process.  So, we get custom chips, and they get incredible experience actually doing part of a chip design.  Usually, the prof and 2 students do the whole design, simulation, layout, etc.  You don't have to actually DRAW every feature of the transistor.  You tell the tools the size (length and width) and the design kit puts out the complicated interdigitated structure.  You then plant the transistor where you want it, and wire it up.

Still, it is VERY much slower than PC board layout, possibly 100X slower.  A prototype PC board will cost a few hundred $ and take you a week or two to build and find the errors.  The ASIC costs tens of K $, takes months to come back from the foundry, then you have to make a test board to power up the chip and see if it works.

Jon
 
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Offline Kjelt

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Re: Chip making process
« Reply #39 on: October 15, 2018, 07:40:43 pm »
I had a "chip process"intro course two years ago, just looked through the notes, the costs are staggering.
The design (only the design) costs as rule of thumb $1/transistor, the examples given all had more than 100M transistors so I guess for lower amounts of transistors this might be much higher.
The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.
Don't know what your company like to invest but this is not a game for small players.

If you want to follow the course:
 http://www.bitsonchips.com/
« Last Edit: October 15, 2018, 07:43:11 pm by Kjelt »
 
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Offline coppice

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Re: Chip making process
« Reply #40 on: October 15, 2018, 08:06:50 pm »
I had a "chip process"intro course two years ago, just looked through the notes, the costs are staggering.
The design (only the design) costs as rule of thumb $1/transistor, the examples given all had more than 100M transistors so I guess for lower amounts of transistors this might be much higher.
The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.
Don't know what your company like to invest but this is not a game for small players.

If you want to follow the course:
 http://www.bitsonchips.com/
Prices for state of the art reticles are way above the prices for the kinds of geometries used for most analogue and mixed signal work. You still need deep pockets, though, especially if there are errors on the first pass (highly likely) that can't be fixed by changing just a metalisation layer. Defensive design approaches help a lot with this. If you put suitable spare stuff on the die, its much more likely that a metalisation fix can be used to patch in some of those spare bits to fix an error.
« Last Edit: October 15, 2018, 08:11:43 pm by coppice »
 

Offline amyk

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Re: Chip making process
« Reply #41 on: October 16, 2018, 02:08:51 am »
Do these design kits need to be purchased from the foundry? eg. AMS
The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.
They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.
 

Offline bson

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Re: Chip making process
« Reply #42 on: October 16, 2018, 04:51:39 am »
Not really about the chipmaking process, more like what a chip is made of

https://youtu.be/FMdYuGpPicw
RB has a bunch of interesting videos, I'm surprised he doesn't have more subscribers!  :-+
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #43 on: October 16, 2018, 04:58:30 am »
Do these design kits need to be purchased from the foundry? eg. AMS
The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.
They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.
Plus additional info in the sheet says
OnSemi > 20 samples
and if your chip fits on 1mm^2 then you would be 20 * 300 = 6000 Euro lighter

Also another footnote given
Price = area (mm2) * price/mm2 with min. fabrication cost equivalent to 4 mm2
Now what would the last line mean?
« Last Edit: October 16, 2018, 05:06:40 am by ZeroResistance »
 

Offline brucehoult

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Re: Chip making process
« Reply #44 on: October 16, 2018, 05:06:52 am »
Do these design kits need to be purchased from the foundry? eg. AMS
The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.
They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.
Plus additional info in the sheet says
OnSemi > 20 samples and
Price = area (mm2) * price/mm2 with min. fabrication cost equivalent to 4 mm2

Now what would the last line mean?

It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #45 on: October 16, 2018, 05:11:33 am »

The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.

So what is the terminology is a reticle = a mask?
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #46 on: October 16, 2018, 05:16:55 am »
It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)
So If my chip fits in 1mm2 and I'm opting for an unpackaged chip would they still charge me for 4mm^2 per chip and that would mean 4 * 300 Eur = Eur 1200 per chip.
and then they require at least 20 samples to be taken so that would be 20 * 1200 = Eur 24000 for an order.
Doesn't the price range sound too heavy for a university or a research setting?
 

Offline brucehoult

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Re: Chip making process
« Reply #47 on: October 16, 2018, 05:22:35 am »
It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)
So If my chip fits in 1mm2 and I'm opting for an unpackaged chip would they still charge me for 4mm^2 per chip and that would mean 4 * 300 Eur = Eur 1200 per chip.
and then they require at least 20 samples to be taken so that would be 20 * 1200 = Eur 24000 for an order.
Doesn't the price range sound too heavy for a university or a research setting?

Packaged or unpackaged is irrelevant to this price. This is, essentially, for your share of making the masks, which is once for all 20 or 40 or 100 chips (depending on the size of the wafers). Plus there's a little bit in there for paying for your part of the wafer and the processing costs, but that's tiny compared to the masks.

So it's EUR 1200, not 20 * 1200.
 

Offline brucehoult

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Re: Chip making process
« Reply #48 on: October 16, 2018, 05:30:17 am »

The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.

So what is the terminology is a reticle = a mask?

Normal terminology, as I understand it, is that a "reticule" is a small square(ish) area that is the maximum size you can make one individual chip. That's how big the masks are. Let's say, for example, that it's 25mm x 25mm or 625 mm^2. Your 1mm x 1mm chip gets put somewhere in this area, and the rest is taken up with other people's chips.

Identical reticules are laid out in a grid covering the whole circular silicon wafer. For a 300mm wafer that's about 100 copies. So you end up with 100 chips. On a 200mm wafer it will be about 40 copies of the reticule (if it's 25mm x 25mm there too).
 
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Offline Kjelt

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Re: Chip making process
« Reply #49 on: October 16, 2018, 09:15:56 am »
So what is the terminology is a reticle = a mask? 
Yes it is.
« Last Edit: October 16, 2018, 09:25:33 am by Kjelt »
 


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