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Offline ZeroResistanceTopic starter

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Chip making process
« on: October 13, 2018, 09:21:13 am »
I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?
2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
4. What tools are required for creating and sending the designs to mask maker and foundry?
5. What are the costs and MOQ involved in the whole process?
6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?

Thanks in Advance!
 

Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #1 on: October 13, 2018, 12:03:13 pm »
I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it

1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?

This is not how ASIC design works. You don't use a TI op-amp, you design your own (or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital). Usually you have a top-down-to-bottom-up design: the team starts with a high level architecture and then starts defining blocks which then have to meet a certain spec. You then use that spec to choose a circuit topology and size your transistors. Then you go back and verify it meets the specs - if you have a lot of excess room you can see if the higher level specs can be tweaked (eg, if you have a power budget of 10 mW, and you planned your output driver to use 2 mW, and your modulator to use 1 mW, but it turns out your output driver spec can be met with just 1 mW, you can allow yourself some more headroom on the modulator).
For digital circuits, the standard way is to use HDL to describe the circuit. Sometimes you manually size bits, but that is not that common (I think - I'm not a digital designer).


2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?

You decide this. There are a lot of factors that go into selecting the technology. Smaller nodes give higher cost per area, but higher density. Analog performance increases, though this has been less and less the case in the last decade. Transitors also behave differently on different technologies - if I take a design from a 0.18 um node, I can't just copy it to 28nm.

Within a technology, you often even select what flavour. What special bells 'n whistles do you want? IO transistors with higher breakdown? How many different VT's do you want? Do you want UTM (ultra-thick metal)? MIM capacitors? How many metal layers? TSVs?


3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?

As stated in 1. this is not how ASIC design works, and hence this is not a problem that exists.

4. What tools are required for creating and sending the designs to mask maker and foundry?

Depends on what you are doing. The industry standard tool for analog ASIC design is Cadence Virtuoso. Costs a lot of money. Like, a lot.

The main tools you tend to use in analog is a spice engine and a layout tool. You first do a design in spice, and then would implement a layout (similar to PCB layout). Depending on the nature of the design, you do PEX (parasitic extraction) to verify you still meet your spec.

If you are into digital, I don't really know what the standard tools are. Usually some logic synthesis tool, and a place-and-route tool (most digital stuff is - mostly - auto-routed).

If you go to RF (my field, so I am a bit more familiar with this), things get more expensive. In addition to all the stuff analog designers use, we use more complicated spice engines (that can do stuff like harmonic balance, periodic steady-state, etc...). The reason for these is because we have very high frequencies and very low frequencies at the same time - the start-up of a VCO can take a lot of time (when compared to the period of the oscillation). The fact that it oscillates at perhaps 20 GHz means that you need a very, very small time step, and as a result you need long simulation times. Special tools can use fancy tricks to get around this.

We also use various types of EM simulators. ADS-Momentum is very common for transformer/inductor design. HFSS is common for on-chip antenna or larger structures.

5. What are the costs and MOQ involved in the whole process?
Depends.

6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?

Thanks in Advance!

My job involves working with Europractice. They do a lot for you. However, I'm not sure how much I can say as a lot of foundry stuff is under NDA. In general you buy area through europractice and then put whatever you want on there (provided it is DRC clean).
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Offline srce

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Re: Chip making process
« Reply #2 on: October 13, 2018, 07:35:20 pm »
4. What tools are required for creating and sending the designs to mask maker and foundry?
Usually a combination of tools from Synopsys, Cadence and Mentor. Typical set might be:

For digital: RTL / gate-level simulation (ModelSim), Synthesis (Design Compiler), Place and Route (IC Compiler), ATPG (TetraMax), STA (PrimeTime), Rail Analysis (PrimeRail), Equivalence checking (Formality)
For analog: Schematic & Layout (Virtuoso), Simulation (Spectre)
For both: DRC / LVS / RCX (Calibre)


5. What are the costs and MOQ involved in the whole process?
The tools mentioned above cost tens of thousands of dollars each!

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

When you go to production, you're looking at millions of dollars for the latest technologies, but old stuff can be a couple of hundred thousand. MOQ is how many die fit on a wafer.

6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own.
They don't make the masks. They just combine the design you send them, with those from other companies, for the MPW, and handle some logistics & customer support etc, so you don't have to deal with the foundry. All you need to do is send Europractice your GDS file (which is an image of each layer of your IC design) and a some cash  :D

 
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Offline srce

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Re: Chip making process
« Reply #3 on: October 13, 2018, 07:38:16 pm »
(or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital).
Yeah, you can get analog IP. But it isn't as portable between different processes as digital, so it's often not available for the exact process you want. This means there's often an extra cost for porting and extra risk given the differences.
 
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Offline srce

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Re: Chip making process
« Reply #4 on: October 13, 2018, 07:40:28 pm »
If you have a real project and some cash, I'd suggest you talk to an ASIC design services company, who will have all the tools and specialise in making ICs for companies who don't have the experience.
 

Offline Richard Crowley

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Re: Chip making process
« Reply #5 on: October 13, 2018, 07:53:49 pm »
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?
All circuits are analog.  There is no such thing as a "digital circuit".  It all depends on how you use it.
All integrated circuits are "flattened to transistors at the lowest level" and resistors and capacitors and inductors and even transformers.
Quote
2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
The layout and masks are created based on the "design rules" of the process. Which implies that you must select the process before you can create the layout and masks.
Quote
3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
You must start with the basic specifications for the input(s) and specifications for the output(s). It benefits nobody to say that you want "a circuilt like a TI-xxx op-amp or Fairchild xxx driver"  What are the actual requirements here.
Quote
4. What tools are required for creating and sending the designs to mask maker and foundry?
As others have mentioned, there are VERY specialized tools used for layout and mask-making. These tools are VERY expensive and only available to people who do enough business to justify the purchase (or lease) cost of this software.
Quote
5. What are the costs and MOQ involved in the whole process?
If you are thinking that you can do this yourself, you can probably forget it.  Unless you have a huge pile of cash and several years to get up to speed.  That is why there are consultants and engineers-for-hire who know the business and can do the layout and mask design.  They know who are the mask vendors and the semiconductor foundries that are best for your particular design.
 
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Online brucehoult

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Re: Chip making process
« Reply #6 on: October 14, 2018, 12:58:50 am »
If you have a real project and some cash, I'd suggest you talk to an ASIC design services company, who will have all the tools and specialise in making ICs for companies who don't have the experience.

Yup. You could try, for example:

https://www.open-silicon.com/
https://en.wikipedia.org/wiki/Open-Silicon

[Disclaimer: acquired this year by my employer SiFive]
 

Offline radiogeek381

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Re: Chip making process
« Reply #7 on: October 15, 2018, 01:19:26 am »
To give you an idea what a "modest" chip development project for an SOC  circa 2005 entailed:

Project:
an SOC with
6 processor cores
24 channels of SERDES Inputs
24 channels of SERDES outputs
2 DIMM controllers
PCI express root complex
6 coherent cache modules

Staffing:
3 architects
10 validation engineers
6 logic designers (they also did synthesis, place & route, and global integration)
1 manager

External IP
DRAM controller
DRAM phy
SERDES blocks
PCIexpress controller/phy
PLL blocks

CAD tools:
RTL synthesis
Place & Route
DRC checkers
SPICE
Timing validation tools
Verilog simulation tools
Formal validation tools

Time on task: 18 months.

Total expenses ~$15M to 18M US. (not including the processor instruction set architecture license)

Of that about $2M was for CAD tools alone, and we got an extremely good price due to some relationships.

Another $1.5M was spent on the IP block buyouts.

FAB, mask, testing, and prototype lot fees amounted to about $2M.

And this didn't include the cost of office space, workstations, server rooms, system prototypes, and all the other things that go into supporting an engineering team. Nor did it include the system engineers (that made the big box with the wheels and fans and power supplies and cables) the software team (that made it all go) and the executive team (that raised the money, paid the bills, found the customers, closed the sales, and such).

And the intervening years have not made things much simpler or much cheaper. Tools cost money. People to fly them cost money. Other people's intellectual property costs money.

There are smaller SOC efforts, but not many with industrial markets -- this chip was going into a large computing system. And this was a small SOC effort -- as remote in scale from something like a Xeon as a wheel barrow is from a dump truck. A typical big-time large server chip will take hundreds of person-years to bring to market.


Others may have participated in different efforts that had smaller (or larger) budgets and costs, but this is a datapoint, and not far from typical. Academic projects are cheaper because
  • They don't pay for labor
  • They don't pay for CAD tools
  • They don't generally pay industrial prices for IP licenses
  • They probably don't spend as much in validation


In general, an ASIC doesn't really pay unless you're talking about enough sales to offset the NRE -- so if you are looking at an SOC, there better be lots more than $20M in likely revenue (like 5x more...) or you'll have trouble making a competetive business out of it. (If you doubt the 5x multiplier, talk to a finance person, or a bank, or a professional investor. BOM cost is but a small part of getting something out the door and making a profit.)

Small custom analog chips may be different, but NRE doesn't really scale that well with the size of the die.  MOSIS and such are nice, but they don't do production. Eventually you need to contract with a FAB or an intermediary. (It will likely be an intermediary, as TSMC and others don't normally deal with small (say, less than $1B?) operations.

So, what is there to do? Over the past 30+ years I've seen several models:
  • Use an off-the-shelf solution. Most applications can't justify the expense of custom solutions.
  •    Find a vendor that has something close to the requirement and negotiate a "special version." (This is a comon approach in SOC markets, and is often the reason for lots of variants for one product.)
  • (For digital applications) Use an FPGA or other configurable solution. (This often works out well for product volumes up into the ~100K units range.  Much depends on your ability to negotiate terms and prices with a vendor.
  • Contract custom development to a design services organization. This can range from handing them a product requirements document all the way to giving them RTL or completed layout. Your internal cost rise as the handoff gets closer to the chip, your contracting costs rise the more you hand over to the design house. 
  • Do it yourself.  There are a few heroic industrial projects that have done this on a shoestring, but the principals were able to finance the development out-of-pocket, and were tremendously talented, experienced, and lucky. (And they knew how to make their own luck.) In general, resist the temptation to assume "you can do it cheaper" because if you haven't done it before, you can't.
     


Analog custom parts are outside my experience, but the cost in IP, tools, bodies, and FAB will still be significant.  The tough part is that the custom silicon industry is built primarily to support digital designs, not analog.  In particular, though "all digital circuits are really analog," over the past 50 years the industry has built lots of tools and practices that abstract the analog parts away for most of the digital design task. (Yes, I know about timing validation, signal integrity, electromigration, power net modeling, clock distribution, thermal modeling, and IO design rules -- I have all those merit badges.  Nonetheless, in modern synthesized designs, much of this is taken care of "under the covers" by CAD tools or design specialists. This is part of the de-skilling of the industry (sadly for those of us who know about TV, SI, EM, power...) and for the dramatic rise in productivity (good for everybody else).

I have worked with analog design houses, and they use many of the same tools as the digital folks, but have much more complex relationships with the foundry (or foundries) and often will push a test chip or two through the process before they are ready for prime time.

All that said, building custom or semi-custom chips is a hoot. (But it is a very expensive hoot.)
 
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Offline coppice

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Re: Chip making process
« Reply #8 on: October 15, 2018, 01:32:08 am »
All that said, building custom or semi-custom chips is a hoot. (But it is a very expensive hoot.)
Yeah, its all fun until you're on a fine process and need an ALR (all layers revision) of the mask set.  :)
 

Online Alex Eisenhut

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Re: Chip making process
« Reply #9 on: October 15, 2018, 01:49:05 am »
Not really about the chipmaking process, more like what a chip is made of

https://youtu.be/FMdYuGpPicw

I think he even posts here.

If you want a good video on the fab process, this one's great

Hoarder of 8-bit Commodore relics and 1960s Tektronix 500-series stuff. Unconventional interior decorator.
 
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Online brucehoult

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Re: Chip making process
« Reply #10 on: October 15, 2018, 03:57:36 am »
So, what is there to do? Over the past 30+ years I've seen several models:
  • Use an off-the-shelf solution. Most applications can't justify the expense of custom solutions.
  •    Find a vendor that has something close to the requirement and negotiate a "special version." (This is a comon approach in SOC markets, and is often the reason for lots of variants for one product.)
  • (For digital applications) Use an FPGA or other configurable solution. (This often works out well for product volumes up into the ~100K units range.  Much depends on your ability to negotiate terms and prices with a vendor.
  • Contract custom development to a design services organization. This can range from handing them a product requirements document all the way to giving them RTL or completed layout. Your internal cost rise as the handoff gets closer to the chip, your contracting costs rise the more you hand over to the design house. 
  • Do it yourself.  There are a few heroic industrial projects that have done this on a shoestring, but the principals were able to finance the development out-of-pocket, and were tremendously talented, experienced, and lucky. (And they knew how to make their own luck.) In general, resist the temptation to assume "you can do it cheaper" because if you haven't done it before, you can't.
     

Coming soon (months, not years): SiFive Chip Designer https://www.sifive.com/chip-designer

Choose a set of preconfigured CPU cores, or customise your own with SiFive Core designer (https://scs.sifive.com/core-designer/). Add both SiFive and 3rd party IP blocks (hundreds to choose from). The IP blocks are free to use for prototype chips (shuttle runs).

The public pages are not live yet but the flow has been tested internally to recreate the FU540 (64 bit quad+one core 1.5 GHz ) from scratch and through into TSMC's flow and taped out. It works.

The vision:

[Disclaimer: I liked what they're doing so much I joined the company]
 
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Online amyk

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Re: Chip making process
« Reply #11 on: October 15, 2018, 04:04:22 am »
I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #12 on: October 15, 2018, 05:48:46 am »

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.
2. So how many transistors make a gate ?
3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #13 on: October 15, 2018, 05:52:33 am »
All circuits are analog.  There is no such thing as a "digital circuit".  It all depends on how you use it.
All integrated circuits are "flattened to transistors at the lowest level" and resistors and capacitors and inductors and even transformers.

From what I read here
https://semiengineering.com/analogs-unfair-disadvantage/,
They say that for analog chips smaller size increases certain issues? So there might be certain differences in an analog process and digital process.
« Last Edit: October 15, 2018, 06:39:49 am by ZeroResistance »
 

Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #14 on: October 15, 2018, 05:53:17 am »
I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....
Any idea which chinese foundries?
 

Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #15 on: October 15, 2018, 06:18:08 am »

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.

The thing is that not all transistors are the same size - something which is even more so the case for analog design. Just because you can make a tiny 200nmx30nm transistor, doesn't mean that you want to. Matching, gain, noise, all are reasons why you want to play around with sizes.

2. So how many transistors make a gate ?

Depends on the gate. Ranges from two (inventor) to a few dozen.

3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.

You can't do this because it all depends on specs. For obvious reasons, making a simple opamp that has little gain, poor offset, and works to 200 kHz will be a lot easier to design than a high-performance 2 GHz GBW amplifier. You can always look up a few standard opamp/OTA configurations to get a ball-park idea but even then you can't really say much.

The fact that digital logic is getting a lot smaller, and as a result calibration is being applied /everywhere/ (calibrate out offsets etc) this only gets more complex.

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

The best part about magic is when it stops being magic and becomes science instead

"There was no road, but the people walked on it, and the road came to be, and the people followed it, for the road took the path of least resistance"
 
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Offline ZeroResistanceTopic starter

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Re: Chip making process
« Reply #16 on: October 15, 2018, 06:41:29 am »
How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?
 

Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #17 on: October 15, 2018, 06:45:12 am »
How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

There are special processes used often for power electronics or automotive. These tend to have much higher breakdown voltages. Though there are some things you can do with modern CMOS, it's hard. (and I've only ever seen it done for applications where it has to be a single-chip solution because of volume (length-times-width-times-height volume, not amount of chips) and weight reasons. What is also possible is a multiple-dies-in-package solution, where you will combine a CMOS die with a power-fet die inside a single package.
The best part about magic is when it stops being magic and becomes science instead

"There was no road, but the people walked on it, and the road came to be, and the people followed it, for the road took the path of least resistance"
 
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Offline mikeselectricstuff

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Re: Chip making process
« Reply #18 on: October 15, 2018, 08:11:11 am »
If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.
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Offline srce

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Re: Chip making process
« Reply #19 on: October 15, 2018, 08:41:21 am »
If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.
Older processes analog processes are much cheaper. You could knock out a design for under $100k, including tools. But even if for more modern processes, it's still possible to make very cheap parts, providing you are selling millions of them. Because although the NRE costs are high, the actual cost per mm of silicon is low  (E.g. a couple of $k per wafer, depending on the process).
 

Offline srce

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Re: Chip making process
« Reply #20 on: October 15, 2018, 08:49:30 am »
I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....
Any idea which chinese foundries?
SMIC. But, lots of have partner programs (E.g. https://www.globalfoundries.com/design-services/fdxcelerator-partner-program) that potentially could be persuaded if you have some really interesting IP. They're not going to do it for fun, though.

 
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Offline srce

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Re: Chip making process
« Reply #21 on: October 15, 2018, 08:58:33 am »
1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.
Look on these pages: http://www.europractice-ic.com/technologies_TSMC.php?tech_id=90nm and look through the different nodes for Gate density.

2. So how many transistors make a gate ?
gate count is usually lowest drive strength, 2-input NAND equivalent rather than transistor counts (So 1 gate = 4 transistors).

3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.
It's not just about transistors though. In analog blocks, much of the area will be for capacitors and resistors - these don't scale much between processes. (E.g. capacitance is roughly proportional to area, so it doesn't matter what process you are using (to a first order)).
 
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Offline srce

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Re: Chip making process
« Reply #22 on: October 15, 2018, 09:01:07 am »
[Disclaimer: I liked what they're doing so much I joined the company]
How many licensees do you have now?
 

Offline srce

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Re: Chip making process
« Reply #23 on: October 15, 2018, 09:03:59 am »
How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?
What voltages? You'll probably need something specialised: https://www.xfab.com/markets/applications/high-voltage/
 
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Online brucehoult

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Re: Chip making process
« Reply #24 on: October 15, 2018, 09:17:01 am »
[Disclaimer: I liked what they're doing so much I joined the company]
How many licensees do you have now?

I don't know exactly, and I wouldn't be allowed to say anyway :-) Certainly a lot more than have publicly announced products, which is something that just started to happen in August. The pipeline from deal to announced/shipping product can be quite long. And definitely there are licencees who will never make any public announcement about it.

Some who have announced to date:

FADU: enterprise SSD controller in 7nm with multiple E51s (64 bit, no MMU) https://www.prnewswire.com/news-releases/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip-300693176.html

Mobiveil: E51 and U54 complex (similar to the HiFive Unleashed board) embedded in an FPGA as a configurable SSD controller https://www.prnewswire.com/news-releases/mobiveil-inc-and-sifive-inc-partner-to-develop-risc-v-based-configurable-ssd-platform-for-data-center-and-enterprise-storage-applications-300693280.html

eSilicon: E2-series core (32 bit, 2-stage pipeline), in SerDes applications. This one is in 7 nm FinFET https://www.prnewswire.com/news-releases/esilicon-licenses-industry-leading-sifive-e2-core-ip-for-next-generation-serdes-ip-300692833.html

Huami: E31 based SoC for IoT/fitness applications https://abopen.com/news/huami-announces-risc-v-based-fitness-wearables-smartwatch/

Of course Western Digital is well known to be a customer and investor in SiFive.
 


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