Chip making process

[ZeroResistance]

I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?
2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
4. What tools are required for creating and sending the designs to mask maker and foundry?
5. What are the costs and MOQ involved in the whole process?
6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?

Thanks in Advance!

[TheUnnamedNewbie]

I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it

1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?

This is not how ASIC design works. You don't use a TI op-amp, you design your own (or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital). Usually you have a top-down-to-bottom-up design: the team starts with a high level architecture and then starts defining blocks which then have to meet a certain spec. You then use that spec to choose a circuit topology and size your transistors. Then you go back and verify it meets the specs - if you have a lot of excess room you can see if the higher level specs can be tweaked (eg, if you have a power budget of 10 mW, and you planned your output driver to use 2 mW, and your modulator to use 1 mW, but it turns out your output driver spec can be met with just 1 mW, you can allow yourself some more headroom on the modulator).
For digital circuits, the standard way is to use HDL to describe the circuit. Sometimes you manually size bits, but that is not that common (I think - I'm not a digital designer).

2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?

You decide this. There are a lot of factors that go into selecting the technology. Smaller nodes give higher cost per area, but higher density. Analog performance increases, though this has been less and less the case in the last decade. Transitors also behave differently on different technologies - if I take a design from a 0.18 um node, I can't just copy it to 28nm.

Within a technology, you often even select what flavour. What special bells 'n whistles do you want? IO transistors with higher breakdown? How many different VT's do you want? Do you want UTM (ultra-thick metal)? MIM capacitors? How many metal layers? TSVs?

3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?

As stated in 1. this is not how ASIC design works, and hence this is not a problem that exists.

4. What tools are required for creating and sending the designs to mask maker and foundry?

Depends on what you are doing. The industry standard tool for analog ASIC design is Cadence Virtuoso. Costs a lot of money. Like, a lot.

The main tools you tend to use in analog is a spice engine and a layout tool. You first do a design in spice, and then would implement a layout (similar to PCB layout). Depending on the nature of the design, you do PEX (parasitic extraction) to verify you still meet your spec.

If you are into digital, I don't really know what the standard tools are. Usually some logic synthesis tool, and a place-and-route tool (most digital stuff is - mostly - auto-routed).

If you go to RF (my field, so I am a bit more familiar with this), things get more expensive. In addition to all the stuff analog designers use, we use more complicated spice engines (that can do stuff like harmonic balance, periodic steady-state, etc...). The reason for these is because we have very high frequencies and very low frequencies at the same time - the start-up of a VCO can take a lot of time (when compared to the period of the oscillation). The fact that it oscillates at perhaps 20 GHz means that you need a very, very small time step, and as a result you need long simulation times. Special tools can use fancy tricks to get around this.

We also use various types of EM simulators. ADS-Momentum is very common for transformer/inductor design. HFSS is common for on-chip antenna or larger structures.

5. What are the costs and MOQ involved in the whole process?

Depends.

6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?

Thanks in Advance!

My job involves working with Europractice. They do a lot for you. However, I'm not sure how much I can say as a lot of foundry stuff is under NDA. In general you buy area through europractice and then put whatever you want on there (provided it is DRC clean).

[srce]

4. What tools are required for creating and sending the designs to mask maker and foundry?

Usually a combination of tools from Synopsys, Cadence and Mentor. Typical set might be:

For digital: RTL / gate-level simulation (ModelSim), Synthesis (Design Compiler), Place and Route (IC Compiler), ATPG (TetraMax), STA (PrimeTime), Rail Analysis (PrimeRail), Equivalence checking (Formality)
For analog: Schematic & Layout (Virtuoso), Simulation (Spectre)
For both: DRC / LVS / RCX (Calibre)

5. What are the costs and MOQ involved in the whole process?

The tools mentioned above cost tens of thousands of dollars each!

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

When you go to production, you're looking at millions of dollars for the latest technologies, but old stuff can be a couple of hundred thousand. MOQ is how many die fit on a wafer.

6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own.

They don't make the masks. They just combine the design you send them, with those from other companies, for the MPW, and handle some logistics & customer support etc, so you don't have to deal with the foundry. All you need to do is send Europractice your GDS file (which is an image of each layer of your IC design) and a some cash 

[srce]

(or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital).

Yeah, you can get analog IP. But it isn't as portable between different processes as digital, so it's often not available for the exact process you want. This means there's often an extra cost for porting and extra risk given the differences.

[srce]

If you have a real project and some cash, I'd suggest you talk to an ASIC design services company, who will have all the tools and specialise in making ICs for companies who don't have the experience.

[Richard Crowley]

1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?

All circuits are analog.  There is no such thing as a "digital circuit".  It all depends on how you use it.
All integrated circuits are "flattened to transistors at the lowest level" and resistors and capacitors and inductors and even transformers.

2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?

The layout and masks are created based on the "design rules" of the process. Which implies that you must select the process before you can create the layout and masks.

3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?

You must start with the basic specifications for the input(s) and specifications for the output(s). It benefits nobody to say that you want "a circuilt like a TI-xxx op-amp or Fairchild xxx driver"  What are the actual requirements here.

4. What tools are required for creating and sending the designs to mask maker and foundry?

As others have mentioned, there are VERY specialized tools used for layout and mask-making. These tools are VERY expensive and only available to people who do enough business to justify the purchase (or lease) cost of this software.

5. What are the costs and MOQ involved in the whole process?

If you are thinking that you can do this yourself, you can probably forget it.  Unless you have a huge pile of cash and several years to get up to speed.  That is why there are consultants and engineers-for-hire who know the business and can do the layout and mask design.  They know who are the mask vendors and the semiconductor foundries that are best for your particular design.

[brucehoult]

If you have a real project and some cash, I'd suggest you talk to an ASIC design services company, who will have all the tools and specialise in making ICs for companies who don't have the experience.

Yup. You could try, for example:

https://www.open-silicon.com/
https://en.wikipedia.org/wiki/Open-Silicon

[Disclaimer: acquired this year by my employer SiFive]

[radiogeek381]

To give you an idea what a "modest" chip development project for an SOC  circa 2005 entailed:

Project:
an SOC with
6 processor cores
24 channels of SERDES Inputs
24 channels of SERDES outputs
2 DIMM controllers
PCI express root complex
6 coherent cache modules

Staffing:
3 architects
10 validation engineers
6 logic designers (they also did synthesis, place & route, and global integration)
1 manager

External IP
DRAM controller
DRAM phy
SERDES blocks
PCIexpress controller/phy
PLL blocks

CAD tools:
RTL synthesis
Place & Route
DRC checkers
SPICE
Timing validation tools
Verilog simulation tools
Formal validation tools

Time on task: 18 months.

Total expenses ~$15M to 18M US. (not including the processor instruction set architecture license)

Of that about $2M was for CAD tools alone, and we got an extremely good price due to some relationships.

Another $1.5M was spent on the IP block buyouts.

FAB, mask, testing, and prototype lot fees amounted to about $2M.

And this didn't include the cost of office space, workstations, server rooms, system prototypes, and all the other things that go into supporting an engineering team. Nor did it include the system engineers (that made the big box with the wheels and fans and power supplies and cables) the software team (that made it all go) and the executive team (that raised the money, paid the bills, found the customers, closed the sales, and such).

And the intervening years have not made things much simpler or much cheaper. Tools cost money. People to fly them cost money. Other people's intellectual property costs money.

There are smaller SOC efforts, but not many with industrial markets -- this chip was going into a large computing system. And this was a small SOC effort -- as remote in scale from something like a Xeon as a wheel barrow is from a dump truck. A typical big-time large server chip will take hundreds of person-years to bring to market.


Others may have participated in different efforts that had smaller (or larger) budgets and costs, but this is a datapoint, and not far from typical. Academic projects are cheaper because

• They don't pay for labor
• They don't pay for CAD tools
• They don't generally pay industrial prices for IP licenses
• They probably don't spend as much in validation

In general, an ASIC doesn't really pay unless you're talking about enough sales to offset the NRE -- so if you are looking at an SOC, there better be lots more than $20M in likely revenue (like 5x more...) or you'll have trouble making a competetive business out of it. (If you doubt the 5x multiplier, talk to a finance person, or a bank, or a professional investor. BOM cost is but a small part of getting something out the door and making a profit.)

Small custom analog chips may be different, but NRE doesn't really scale that well with the size of the die.  MOSIS and such are nice, but they don't do production. Eventually you need to contract with a FAB or an intermediary. (It will likely be an intermediary, as TSMC and others don't normally deal with small (say, less than $1B?) operations.

So, what is there to do? Over the past 30+ years I've seen several models:

• Use an off-the-shelf solution. Most applications can't justify the expense of custom solutions.
•    Find a vendor that has something close to the requirement and negotiate a "special version." (This is a comon approach in SOC markets, and is often the reason for lots of variants for one product.)
• (For digital applications) Use an FPGA or other configurable solution. (This often works out well for product volumes up into the ~100K units range.  Much depends on your ability to negotiate terms and prices with a vendor.
• Contract custom development to a design services organization. This can range from handing them a product requirements document all the way to giving them RTL or completed layout. Your internal cost rise as the handoff gets closer to the chip, your contracting costs rise the more you hand over to the design house. 
• Do it yourself.  There are a few heroic industrial projects that have done this on a shoestring, but the principals were able to finance the development out-of-pocket, and were tremendously talented, experienced, and lucky. (And they knew how to make their own luck.) In general, resist the temptation to assume "you can do it cheaper" because if you haven't done it before, you can't.
   

Analog custom parts are outside my experience, but the cost in IP, tools, bodies, and FAB will still be significant.  The tough part is that the custom silicon industry is built primarily to support digital designs, not analog.  In particular, though "all digital circuits are really analog," over the past 50 years the industry has built lots of tools and practices that abstract the analog parts away for most of the digital design task. (Yes, I know about timing validation, signal integrity, electromigration, power net modeling, clock distribution, thermal modeling, and IO design rules -- I have all those merit badges.  Nonetheless, in modern synthesized designs, much of this is taken care of "under the covers" by CAD tools or design specialists. This is part of the de-skilling of the industry (sadly for those of us who know about TV, SI, EM, power...) and for the dramatic rise in productivity (good for everybody else).

I have worked with analog design houses, and they use many of the same tools as the digital folks, but have much more complex relationships with the foundry (or foundries) and often will push a test chip or two through the process before they are ready for prime time.

All that said, building custom or semi-custom chips is a hoot. (But it is a very expensive hoot.)

[coppice]

All that said, building custom or semi-custom chips is a hoot. (But it is a very expensive hoot.)

Yeah, its all fun until you're on a fine process and need an ALR (all layers revision) of the mask set. 

[Alex Eisenhut]

Not really about the chipmaking process, more like what a chip is made of

https://youtu.be/FMdYuGpPicw

I think he even posts here.

If you want a good video on the fab process, this one's great

[brucehoult]

So, what is there to do? Over the past 30+ years I've seen several models:

• Use an off-the-shelf solution. Most applications can't justify the expense of custom solutions.
•    Find a vendor that has something close to the requirement and negotiate a "special version." (This is a comon approach in SOC markets, and is often the reason for lots of variants for one product.)
• (For digital applications) Use an FPGA or other configurable solution. (This often works out well for product volumes up into the ~100K units range.  Much depends on your ability to negotiate terms and prices with a vendor.
• Contract custom development to a design services organization. This can range from handing them a product requirements document all the way to giving them RTL or completed layout. Your internal cost rise as the handoff gets closer to the chip, your contracting costs rise the more you hand over to the design house. 
• Do it yourself.  There are a few heroic industrial projects that have done this on a shoestring, but the principals were able to finance the development out-of-pocket, and were tremendously talented, experienced, and lucky. (And they knew how to make their own luck.) In general, resist the temptation to assume "you can do it cheaper" because if you haven't done it before, you can't.
   

Coming soon (months, not years): SiFive Chip Designer https://www.sifive.com/chip-designer

Choose a set of preconfigured CPU cores, or customise your own with SiFive Core designer (https://scs.sifive.com/core-designer/). Add both SiFive and 3rd party IP blocks (hundreds to choose from). The IP blocks are free to use for prototype chips (shuttle runs).

The public pages are not live yet but the flow has been tested internally to recreate the FU540 (64 bit quad+one core 1.5 GHz ) from scratch and through into TSMC's flow and taped out. It works.

The vision:

[Disclaimer: I liked what they're doing so much I joined the company]

[amyk]

I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....

[ZeroResistance]

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.
2. So how many transistors make a gate ?
3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.

[ZeroResistance]

All circuits are analog.  There is no such thing as a "digital circuit".  It all depends on how you use it.
All integrated circuits are "flattened to transistors at the lowest level" and resistors and capacitors and inductors and even transformers.

From what I read here
https://semiengineering.com/analogs-unfair-disadvantage/,
They say that for analog chips smaller size increases certain issues? So there might be certain differences in an analog process and digital process.

[ZeroResistance]

I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....

Any idea which chinese foundries?

[TheUnnamedNewbie]

For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf

1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.

The thing is that not all transistors are the same size - something which is even more so the case for analog design. Just because you can make a tiny 200nmx30nm transistor, doesn't mean that you want to. Matching, gain, noise, all are reasons why you want to play around with sizes.

2. So how many transistors make a gate ?

Depends on the gate. Ranges from two (inventor) to a few dozen.

3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.

You can't do this because it all depends on specs. For obvious reasons, making a simple opamp that has little gain, poor offset, and works to 200 kHz will be a lot easier to design than a high-performance 2 GHz GBW amplifier. You can always look up a few standard opamp/OTA configurations to get a ball-park idea but even then you can't really say much.

The fact that digital logic is getting a lot smaller, and as a result calibration is being applied /everywhere/ (calibrate out offsets etc) this only gets more complex.

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

[ZeroResistance]

How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

[TheUnnamedNewbie]

How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

There are special processes used often for power electronics or automotive. These tend to have much higher breakdown voltages. Though there are some things you can do with modern CMOS, it's hard. (and I've only ever seen it done for applications where it has to be a single-chip solution because of volume (length-times-width-times-height volume, not amount of chips) and weight reasons. What is also possible is a multiple-dies-in-package solution, where you will combine a CMOS die with a power-fet die inside a single package.

[mikeselectricstuff]

If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.

[srce]

If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.

Older processes analog processes are much cheaper. You could knock out a design for under $100k, including tools. But even if for more modern processes, it's still possible to make very cheap parts, providing you are selling millions of them. Because although the NRE costs are high, the actual cost per mm of silicon is low  (E.g. a couple of $k per wafer, depending on the process).

[srce]

I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....

Any idea which chinese foundries?

SMIC. But, lots of have partner programs (E.g. https://www.globalfoundries.com/design-services/fdxcelerator-partner-program) that potentially could be persuaded if you have some really interesting IP. They're not going to do it for fun, though.

[srce]

1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.

Look on these pages: http://www.europractice-ic.com/technologies_TSMC.php?tech_id=90nm and look through the different nodes for Gate density.

2. So how many transistors make a gate ?

gate count is usually lowest drive strength, 2-input NAND equivalent rather than transistor counts (So 1 gate = 4 transistors).

3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.

It's not just about transistors though. In analog blocks, much of the area will be for capacitors and resistors - these don't scale much between processes. (E.g. capacitance is roughly proportional to area, so it doesn't matter what process you are using (to a first order)).

[srce]

[Disclaimer: I liked what they're doing so much I joined the company]

How many licensees do you have now?

[srce]

How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

What voltages? You'll probably need something specialised: https://www.xfab.com/markets/applications/high-voltage/

[brucehoult]

[Disclaimer: I liked what they're doing so much I joined the company]

How many licensees do you have now?

I don't know exactly, and I wouldn't be allowed to say anyway :-) Certainly a lot more than have publicly announced products, which is something that just started to happen in August. The pipeline from deal to announced/shipping product can be quite long. And definitely there are licencees who will never make any public announcement about it.

Some who have announced to date:

FADU: enterprise SSD controller in 7nm with multiple E51s (64 bit, no MMU) https://www.prnewswire.com/news-releases/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip-300693176.html

Mobiveil: E51 and U54 complex (similar to the HiFive Unleashed board) embedded in an FPGA as a configurable SSD controller https://www.prnewswire.com/news-releases/mobiveil-inc-and-sifive-inc-partner-to-develop-risc-v-based-configurable-ssd-platform-for-data-center-and-enterprise-storage-applications-300693280.html

eSilicon: E2-series core (32 bit, 2-stage pipeline), in SerDes applications. This one is in 7 nm FinFET https://www.prnewswire.com/news-releases/esilicon-licenses-industry-leading-sifive-e2-core-ip-for-next-generation-serdes-ip-300692833.html

Huami: E31 based SoC for IoT/fitness applications https://abopen.com/news/huami-announces-risc-v-based-fitness-wearables-smartwatch/

Of course Western Digital is well known to be a customer and investor in SiFive.

[amyk]

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.

[mikeselectricstuff]

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

[coppice]

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

See the sot23-6 PICs for an example. I don't think the die of those are larger than 1mm^2.

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

Since those devices run at 5V, and presumably do not regulate inside the chip, they are probably on a 500nm or 800nm process. That does push the size up quite a lot, even for such a simple chip.

[mikeselectricstuff]

I'm pretty sure the 10F322 uses a lower core voltage internally - there is an internal regulator "which provides operation above 3.6v" according to the datasheet

[coppice]

I'm pretty sure the 10F322 uses a lower core voltage internally - there is an internal regulator "which provides operation above 3.6v" according to the datasheet

I missed that. If they are regulating to run the core at a maximum of 3.6V its probably a 350nm process.

[jmelson]

I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?

I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.

Yes, certainly, transistors are the basic element.  But, actually, there is a lower level, which is the individual layer masks.

Will the same be applicable for digital circuits?

Yes, at the lowest level, it is all analog, and all transistors, resistors and wires.

2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?

Yes, you must select a process first, to have the parameters of the silicon, doping, etc. before you can start describing the transistor channel width and length.
Each transistor is described by length, width and type (doping).  Each process has a "design kit' which has all these specs.

3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?

You really CAN'T!  These are proprietary parts, and TI, etc. will not give out the internal design.  So, you have to redesign these parts in the process you select.
Then, simulate until the performance is what you want.

4. What tools are required for creating and sending the designs to mask maker and foundry?

There are several major programs.  If you are not at a university, the commercial design suites are very expensive, like 50K US dollars/seat, with massive costs to renew each year.   Cadence is the leader, Mentor is still used, I think.   There are also some open-source design packages.

5. What are the costs and MOQ involved in the whole process?

I am involved in a university project making chips for nuclear physics experiments.  We use MOSIS, and a university Cadence license.  We used to use the AMI (now ON Semi) C5 process, a 350 nm 5V process.  We just did our first chip with the Austria Semi (AMS) fab.  Their design kit is WAY better than the AMI/ON Semi kit.  Minimum order is 40 parts (untested) and you can order more in 40-part increments.  Our chip was fairly large, about 5 x 7 mm, and the cost for 40 parts would run some $28K US dollars, unpackaged.  They usually charge something like $7500 for packaging.

6. I have heard  of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?

Well, MOSIS combines dozens of masks from different projects onto one wafer, and thus spreads the cost of the masks across multiple projects.
So, you must provide them the mask layers, generally as a "Calma stream", and they have to meet a number of criteria to be acceptable for fabrication.
If the mask data is accepted, then MOSIS handles the whole interaction with the fab.

Jon

[ZeroResistance]

We use MOSIS, and a university Cadence license.  We used to use the AMI (now ON Semi) C5 process, a 350 nm 5V process.  We just did our first chip with the Austria Semi (AMS) fab.  Their design kit is WAY better than the AMI/ON Semi kit.  Minimum order is 40 parts (untested) and you can order more in 40-part increments.  Our chip was fairly large, about 5 x 7 mm, and the cost for 40 parts would run some $28K US dollars, unpackaged.  They usually charge something like $7500 for packaging.

How much time does Mosis take to send you back the chips, once you send them the design files?
How do you handle the unpackaged chips, do they need special care? do you need to pour epoxy on them before testing them? Do they come with pads to solder on the PCB?
How does the software help you in designing the circuit, does it have high level components like op-amps, adc's etc. and them during synthesis these blocks get flattened to transistors?

[jmelson]

How much time does Mosis take to send you back the chips, once you send them the design files?
How do you handle the unpackaged chips, do they need special care? do you need to pour epoxy on them before testing them? Do they come with pads to solder on the PCB?
How does the software help you in designing the circuit, does it have high level components like op-amps, adc's etc. and them during synthesis these blocks get flattened to transistors?

It takes at least 3 months to get the chips back.  Since we require some different packaging (completely filled plastic packages) that costs a few extra weeks.
We do not get unpackaged chips, we always get them packaged.

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon

[ZeroResistance]

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon

Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?

[coppice]

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon

Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?

Unless you can find a canned analogue solution that exactly suits your needs, licensable in a reasonable manner, tailored for the exact process you will use, expect your analogue development to be fairly expensive and protracted.

[Richard Crowley]

Do these design kits need to be purchased from the foundry? eg. AMS

The performance (threshold voltage, speed, current capacity, etc.) of each transistor is inextricably tied to the process parameters.  So, unless you can get something tied to the selected process, you would likely be designing from a lower level.

Its interesting to hear that each transistor in an analog circuit needs to be manually crafted.

Because a transistor of exactly the same dimensions will operate quite differently depending on what process it is made with.  And, of course that applies to ALL circuits.  There are no "digital circuits".

Your would need a quite a big team to make a large circuit wouldn't it?

Define: "large circuit"?  Do you mean 1000s of transistors or billions of transistors?

[Wimberleytech]

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon

Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS
Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?

Unless you can find a canned analogue solution that exactly suits your needs, licensable in a reasonable manner, tailored for the exact process you will use, expect your analogue development to be fairly expensive and protracted.

Just now read through this thread.  Lots of good information and answers.

Lemme make it easy on you.  I will design your chip for you.  Send me the spec (just sketch it on a bar napkin if that is convenient) and I will get started.  Paypal is fine for billing (how well funded is your Paypal account?).
 

[srce]

Do these design kits need to be purchased from the foundry? eg. AMS

The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.

[jmelson]

Some design kits have a lot of stock modules like op-amps included, some do NOT.  You have to get the specific kit to know what will be included.
Otherwise, there are some generic circuits like op-amps that you might be able to download from people.  Well, there is no synthesis for analog parts, that's why each transistor needs to be "carved" to meet your needs.  So, the modules are just a bunch of transistors with dimensions included in them.

Jon

Thanks for the info,
Do these design kits need to be purchased from the foundry? eg. AMS

In general, you have to supply an NDA to MOSIS, they get it approved through the foundry and then you get the design kit, for no extra fee.  I guess that is all rolled into the price at MOSIS.

Its interesting to hear that each transistor in an analog circuit needs to be manually crafted. Your would need a quite a big team to make a large circuit wouldn't it?

Well, no.  We have a professor of IC design, he has masters students, and guides them through the process.  So, we get custom chips, and they get incredible experience actually doing part of a chip design.  Usually, the prof and 2 students do the whole design, simulation, layout, etc.  You don't have to actually DRAW every feature of the transistor.  You tell the tools the size (length and width) and the design kit puts out the complicated interdigitated structure.  You then plant the transistor where you want it, and wire it up.

Still, it is VERY much slower than PC board layout, possibly 100X slower.  A prototype PC board will cost a few hundred $ and take you a week or two to build and find the errors.  The ASIC costs tens of K $, takes months to come back from the foundry, then you have to make a test board to power up the chip and see if it works.

Jon

[Kjelt]

I had a "chip process"intro course two years ago, just looked through the notes, the costs are staggering.
The design (only the design) costs as rule of thumb $1/transistor, the examples given all had more than 100M transistors so I guess for lower amounts of transistors this might be much higher.
The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.
Don't know what your company like to invest but this is not a game for small players.

If you want to follow the course:
 http://www.bitsonchips.com/

[coppice]

I had a "chip process"intro course two years ago, just looked through the notes, the costs are staggering.
The design (only the design) costs as rule of thumb $1/transistor, the examples given all had more than 100M transistors so I guess for lower amounts of transistors this might be much higher.
The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.
Don't know what your company like to invest but this is not a game for small players.

If you want to follow the course:
 http://www.bitsonchips.com/

Prices for state of the art reticles are way above the prices for the kinds of geometries used for most analogue and mixed signal work. You still need deep pockets, though, especially if there are errors on the first pass (highly likely) that can't be fixed by changing just a metalisation layer. Defensive design approaches help a lot with this. If you put suitable spare stuff on the die, its much more likely that a metalisation fix can be used to patch in some of those spare bits to fix an error.

[amyk]

Do these design kits need to be purchased from the foundry? eg. AMS

The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.

They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.

[bson]

Not really about the chipmaking process, more like what a chip is made of

https://youtu.be/FMdYuGpPicw

RB has a bunch of interesting videos, I'm surprised he doesn't have more subscribers! 

[ZeroResistance]

Do these design kits need to be purchased from the foundry? eg. AMS

The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.

They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.
Plus additional info in the sheet says
OnSemi > 20 samples
and if your chip fits on 1mm^2 then you would be 20 * 300 = 6000 Euro lighter

Also another footnote given
Price = area (mm2) * price/mm2 with min. fabrication cost equivalent to 4 mm2
Now what would the last line mean?

[brucehoult]

Do these design kits need to be purchased from the foundry? eg. AMS

The PDKs are usually free - these will often include a standard cell library (e.g. basic AND/OR/NOT gates and Flip Flops) and basic IO cells as well, but not always.

They are free because the fabs make their profits selling ICs, and the design kits help customers to use them to make ICs.

From the price list posted above it looks like ON's 0.7u is the cheapest at the moment, only 300 euro/mm^2. So it is possible to do something for only few k$ now, instead of tens or hundreds of k$.

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.
Plus additional info in the sheet says
OnSemi > 20 samples and
Price = area (mm2) * price/mm2 with min. fabrication cost equivalent to 4 mm2
Now what would the last line mean?

It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)

[ZeroResistance]

The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.

So what is the terminology is a reticle = a mask?

[ZeroResistance]

It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)

So If my chip fits in 1mm2 and I'm opting for an unpackaged chip would they still charge me for 4mm^2 per chip and that would mean 4 * 300 Eur = Eur 1200 per chip.
and then they require at least 20 samples to be taken so that would be 20 * 1200 = Eur 24000 for an order.
Doesn't the price range sound too heavy for a university or a research setting?

[brucehoult]

It means if your chip (including pads, and I expect a mandatory added unused boundary ring) is smaller than 4 mm^2 then you'll be charge for 4 mm^2 anyway. (EUR 1200)

So If my chip fits in 1mm2 and I'm opting for an unpackaged chip would they still charge me for 4mm^2 per chip and that would mean 4 * 300 Eur = Eur 1200 per chip.
and then they require at least 20 samples to be taken so that would be 20 * 1200 = Eur 24000 for an order.
Doesn't the price range sound too heavy for a university or a research setting?

Packaged or unpackaged is irrelevant to this price. This is, essentially, for your share of making the masks, which is once for all 20 or 40 or 100 chips (depending on the size of the wafers). Plus there's a little bit in there for paying for your part of the wafer and the processing costs, but that's tiny compared to the masks.

So it's EUR 1200, not 20 * 1200.

[brucehoult]

The reticles (need two per layer) you need at least 20 depending on the nr of layers, are for the lower layers around $100k/piece upto $300k/piece for state of the art tech.

So what is the terminology is a reticle = a mask?

Normal terminology, as I understand it, is that a "reticule" is a small square(ish) area that is the maximum size you can make one individual chip. That's how big the masks are. Let's say, for example, that it's 25mm x 25mm or 625 mm^2. Your 1mm x 1mm chip gets put somewhere in this area, and the rest is taken up with other people's chips.

Identical reticules are laid out in a grid covering the whole circular silicon wafer. For a 300mm wafer that's about 100 copies. So you end up with 100 chips. On a 200mm wafer it will be about 40 copies of the reticule (if it's 25mm x 25mm there too).

[Kjelt]

So what is the terminology is a reticle = a mask? 

Yes it is.

[brucehoult]

So what is the terminology is a reticle = a mask? 

Yes it is.

I believe in FAB usage mask and reticule are actually alternatives.

A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism.

[ZeroResistance]

So what is the terminology is a reticle = a mask? 

Yes it is.

I believe in FAB usage mask and reticule are actually alternatives.

A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism.

So lets say I send my design to the mask maker and he sends me back a 1mm2 size mask or reticule and for each of the layers.
Or does the mask maker make a grid of the whole design based on what the foundry silicon wafer size is, and and then gives me that for all the layers And then this is submitted to the foundry right? and then they expose the whole wafer at one go and you get he desired number of chips from that wafer.
This would be the process wouldn't it?
In what case would the foundry want to selectively expose a reticule? Because that seems to be a very slow process?

[Kjelt]

I believe in FAB usage mask and reticule are actually alternatives.
A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism. 

I never heard of that. Perhaps in the far past it was done that way with 2" wafers or so but modern stepper scanners contain a reticle holding a single processstep of a single or more dies(chips). This depends on the size of the die. And the wafer is exposed in steps (stepper) or in a scan (scanner) where the reticule and the wafer move in opposite directions (see wiki below).
The whole wafer is so exposed in a couple of scans which totally takes less than 10 seconds.
These machines nowadays do 250 wafers/hour.
https://en.wikipedia.org/wiki/Stepper

BTW the reason is simple you can not focus an entire wafer upto the required nm resolution, your lens would be 1meter diameter and more expensive than the entire fab. The reticule is 4x bigger than the final die so if any dust particle is on the reticle it will not influence the final product.

[Richard Crowley]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die wafer methods using equipment from Perkin-Elmer.  Their optical division developed the Keyhole-9 satellite spy cameras and were later responsible for the Hubble optical system.  When feature sizes started getting smaller, it was getting difficult to expose a whole wafer because minute vibration would blur the image. I remember at one time personnel were deployed as train-spotters to warn of approaching rail traffic so that they could suspend imaging while the train passed.  Giant timbers were wedged between the ground-floor slab and the floor of the fab to reduce the vibration.

As @Kjelt mentioned, current practice is to use 4x reticles to step and repeat exposure across 300mm wafers.  Laser interferometery is used to ensure accurate positioning for each exposure.  And it is good enough that it has operated perfectly during an earthquake. A far cry from the days of wedged timbers and trainspotting.

ED: "whole-wafer", not "whole-die"!

[coppice]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die methods using equipment from Perkin-Elmer.  Their optical division developed the Keyhole-9 satellite spy cameras and were later responsible for the Hubble optical system.  When feature sizes started getting smaller, it was getting difficult to expose a whole wafer because minute vibration would blur the image. I remember at one time personnel were deployed as train-spotters to warn of approaching rail traffic so that they could suspend imaging while the train passed.  Giant timbers were wedged between the ground-floor slab and the floor of the fab to reduce the vibration.

As @Kjelt mentioned, current practice is to use 4x reticles to step and repeat exposure across 300mm wafers.  Laser interferometery is used to ensure accurate positioning for each exposure.  And it is good enough that it has operated perfectly during an earthquake. A far cry from the days of wedged timbers and trainspotting.

The exposure is about the same size now. The active area of the reticule is of the order of 100mm x 100mm.

[srce]

So lets say I send my design to the mask maker and he sends me back a 1mm2 size mask or reticule and for each of the layers.
Or does the mask maker make a grid of the whole design based on what the foundry silicon wafer size is, and and then gives me that for all the layers And then this is submitted to the foundry right? and then they expose the whole wafer at one go and you get he desired number of chips from that wafer.
This would be the process wouldn't it?

For an MPW - you don't have anything to do with masks or reticles. You wont even get to see them. You'll create a GDS file containing the design - send that off - and you'll get dies back in the post. You don't really need to understand anything about the manufacturing process (aside from the purpose of each layer in the GDS file of course )

Generally, IC designers just talk about masks, and don't really care about the distinction. The only time you care, is if your die size is limited by the reticle size, but you shouldn't be anywhere near that.

[srce]

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.

You will get the dies from Europractice in a little tray like this:



You can just forward that to the packaging house, without even opening it. But if you do, because you'll obviously want a look , don't worry, too much, they'll probably survive even if you fiddle with them with tweezers (you can get proper tools). Just don't forget the ESD structures on your IO pads!

Europractice can do packaging - I personally use: http://www.icproto.com/ in the USA. You need to send them a bonding diagram showing how the bond pads should be bonded to the package pins:



And give them some other details like diameter of the bond wires, what metal to use and of course what package you want, and a logo / marking. It will take them about a week (with postage) to do it. A couple of dies may be damaged in the setup process.

You may want to split it in to two lots for packaging, in case you make a mistake in your bonding diagram or they get lost in the post!

You'll need to design the test procedure yourself!

[Wimberleytech]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die methods using equipment from Perkin-Elmer. 

4" single mask (per layer) were common into the 80's.

--I think you meant "whole-wafer" btw.

[Wimberleytech]

In the old days, a reticle was made first from the database.  Using the reticle, a mask was made.  In these photos, you see a retical, the mask that was made from the reticle, and the wafer that was made from the mask (obviously, only one layer is represented).

Somewhere around here, I have a reticle used for a modern step-and-repeat system, but I cannot find it 

Ahaa...here is the reticle

The die is stepped on this redical (5x5) and the 8" wafer is made by stepping this reticle

[ZeroResistance]

You will get the dies from Europractice in a little tray like this:

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

[ZeroResistance]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

[wraper]

You will get the dies from Europractice in a little tray like this:

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

Not only they are too small, why do you think they are solderable in the first place? You can make die it solderable to the PCB but it's a special process.

[ZeroResistance]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

[mikeselectricstuff]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

Faxitron MX20 - unfortunately only does 35kv so barely makes it through the leadframe

[coppice]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Someone like Microchip would not contract for a complete device. They might use an in house fab or they might use a foundry, but the production of the wafers will be one commercial step. They will contract for a specified number of wafers, based on the expected yield of good dies meeting their needs. Next they will send the wafers to an assembly and test place, as a second commercial step, separate from the wafer production. Again this may be an in house operation, or the work may be given to an assembly and test contractor. These two operations - assembly and test - usually go together. You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK. Having the packaging step between two test steps usually leads to them being bundled into an activity at a single site. People like TSMC and UMC are famous as wafer foundries, but there is also a group of less widely known large contract assembly and test companies. The program for the tester will usually be provided and maintained by the chip designers - they are the ones who know what the chip should do, and what needs testing.

Many of the largest silicon companies have no fabs, assembly or test facilities of their own. They do, however, usually have extensive labs of their own. These can get really expensive for a startup, but trying to work without them can be a huge drag on productivity. Things like FIB (focused ion beam) machines don't come cheap, but can be a huge boon when trying to diagnose and work around silicon bugs.

[Wimberleytech]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Here is ballpark based on what a 0.35um flash silicided poly, 4 layers of metal, with cap poly and poly resistor options
Mask costs not included here.

[ZeroResistance]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

[ZeroResistance]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Here is ballpark based on what a 0.35um flash silicided poly, 4 layers of metal, with cap poly and poly resistor options
Mask costs not included here.

This is pretty amazing, did you rattle that off in a few minutes.
Just a bit out of depth with the terminology what does MLO mean? What's is probe yield?
How many wafers do I have to order from the foundry to get these sort of rates?

[coppice]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

Yield depends a LOT on the complexity of the dies and what your pass/fail requirements are. If you have a hard transistor failure you have a dead die, but die may fail because their analogue parts are out of spec, or something won't run at full speed. Your test program can also affect yield, which is something non-obvious to outsiders, but you eventually find can have a real impact on profitability.

For an example, look at the Wimberleytech's information. Hist costs look high, so they may be old. His probe yield and final test yield are reasonable for the geometry and size of die he has, assuming its a tolerant design. An intolerant design (i.e. one where everything has to be just right to pass the production tests) may give much worse yields. If your wafer has only 100 dies they will be huge dies, and the yield will be a lot worse.

[srce]

For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.

They charge a one off fee for the masks, then per wafer.

Packaging would be a seperate expense right?

Yes

[srce]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

Yield depends on process maturity and die size (as well as some other factors) If a wafer only has 100 dies - that suggests they're monster dies and thus the yield would be relatively low. For a more realistic die size on a mature process, you should be looking at 98%. You'll also have a packaging yield as well.

[ZeroResistance]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

Faxitron MX20 - unfortunately only does 35kv so barely makes it through the leadframe

Doesn't the leadframe surround the die, I mean the die is in the center and the leadframe is surrounding it but only on the XY plane? And there is just the plastic packaging on the top.
So just needed to understand how that interfers with the Xray?

[Richard Crowley]

What's is probe yield?

Dice are tested on the wafer before the wafer is sawed apart into dice.
Probe-cards are used to make connection with all the bond-pads so that the die can be tested.
They used to actual put a drop of ink on the bad dice, but now the good/bad information is stored in a database for that wafer.
That way they don't waste time/materials packaging bad dice.

https://www.mjc.co.jp/en/technology/column/probe_card.html

[ZeroResistance]

For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.

They charge a one off fee for the masks, then per wafer.

Packaging would be a seperate expense right?

Yes

Do foundries have a minimum wafer quantity. I mean wemberlytech showed cost of a wafer as USD 1600. So do the foundries expect you to order something like 100 wafers.
And if each wafer has 15000 dies on it. Do the foundries also charge you per die on that wafer.
I guess it should have been area based, if a wafer is 200mm in dia that comes to 31400mm^2. So Do they charge on area of silicon?

[Wimberleytech]

This is pretty amazing, did you rattle that off in a few minutes.
Just a bit out of depth with the terminology what does MLO mean? What's is probe yield?
How many wafers do I have to order from the foundry to get these sort of rates?

This came from my files.  In my former life, I was founder and CTO of a fabless semiconductor company.
MLO = Materials Labor Overhead
Probe yield:  prior to packaging, each die on the wafer is probed and tested.  Only some of these die will pass the probe test...thus the probe yield.
After packaging, the die are tested again.  Less then 100% of the packaged units will yield--package yield.
To work with a foundry, you will have to commit to many thousands of wafers in production.
For this example, I do not recall which package was being used (maybe 32 pin pqfp).

[Wimberleytech]

Do foundries have a minimum wafer quantity. I mean wemberlytech showed cost of a wafer as USD 1600. So do the foundries expect you to order something like 100 wafers.
And if each wafer has 15000 dies on it. Do the foundries also charge you per die on that wafer.
I guess it should have been area based, if a wafer is 200mm in dia that comes to 31400mm^2. So Do they charge on area of silicon?

Foundry does not care how many die.  They charge by the wafer.

[ZeroResistance]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

[Richard Crowley]

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

Depends on what you mean by "soldering".  If you mean using a spool of solder and a soldering iron, forget it.  You are off by a couple orders of magnitude. Your solder will cover 10-20 pads at a time.  For "Chip-on-Board" (COB), they use the same microscopic bond-wire and ultrasonic welding that was used for decades for chip packages.  Then they put a blob of epoxy over the whole thing to protect the die and bond-wires.



In more recent times a process called "flip-chip" is used where pyramids of solder are deposited on the bond-pads.  Then the die is flipped over to face a PC board and the die and board are heated to re-flow the solder to connect all the pads to the board.  In some cases, the raw die is left exposed.  There are YouTube videos showing one of the flip-chips on the Raspberry Pi which turned out to be light-sensitive because it was unprotected and exposed to ambient light.  People taking flash photos would inadvertently reset (or some other problem?) the circuit by the flash of light.

Modern CPUs are packaged this way.  The CPU product is just a small PC board with the die bonded on top, and then a heat-spreader bonded on top of the chip. Frequently decoupling SMD capacitors are on the opposite "bottom" side of the CPU board to get them as close to the chip as possible.  Then all the external connections are implemented with gold-plated pins (Pin-Grid-Array PGA) or lands (Land-Grid-Array LGA)

[Wimberleytech]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

[jmelson]

So what is the terminology is a reticle = a mask?

Way back when, the masks were made to expose the entire wafer in one shot.  That worked up to 50 mm or so wafers.  As wafers got bigger, and dimensions got smaller, they had to go from printing the whole wafer at once, to aligning a smaller reticle onto alignment marks on the wafer, and then step and repeat across the wafer.  The process we have been using uses reticles about 35 mm wide.

So, today, a reticle has some number of chips that are aligned and imaged onto the wafer at one time.  Then, the process is repeated across the wafer.

Jon

[coppice]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

A foundry will happily process a single wafer for you. The price won't be the same as when you run a thousand wafers a month, though.

[ZeroResistance]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

Ok so that makes it 1000 * $1600  per wafer or USD 1.6M per month. But you also do get 15000 dies per wafer or 15000 * 1000 = 15M dies per month.
So per die cost is 15000/1600 that is around $0.11. Seems to be pretty good for a 10F.
But Microchip need to have assured sales right for it to be profitable?
Another issue for Microchip 15M chips per month is a lot, how will they sell that much, they may probably have another deal with the foundry?

[jmelson]

You will get the dies from Europractice in a little tray like this:

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

The bonding pads are something like 40 um square and aluminum.  Not likely you can solder to that!

Jon

[coppice]

Do foundries have a minimum wafer quantity. I mean wemberlytech showed cost of a wafer as USD 1600. So do the foundries expect you to order something like 100 wafers.
And if each wafer has 15000 dies on it. Do the foundries also charge you per die on that wafer.
I guess it should have been area based, if a wafer is 200mm in dia that comes to 31400mm^2. So Do they charge on area of silicon?

In general a foundry doesn't care what is on a wafer. They just process the wafer according to the mask set, ship it to the customer, and charge the agreed wafer price. If the wafer processing went OK, and the number of good die is pretty much in line with expectations, that's the end of the story. If the wafer wasn't processed well, and the yield of good die is low, arguments may ensue. If a large number of wafers have a low yield these arguments might get rather heated. 

[jmelson]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

On one of our designs, we got close to 100% yield, on another we got more like 60%, although the issues were subtle.  That problem was a threshold shift in a chain of amplifiers, a bit of a risky design.

Jon

[Wimberleytech]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

A foundry will happily process a single wafer for you. The price won't be the same as when you run a thousand wafers a month, though.

Have you ever had a foundry run a single wafer for you?

[jmelson]

Do the foundries also charge you per die on that wafer.

There is a cost for the wafer sawing (called singulation), so in large volume, that might be a separate charge.

Jon

[coppice]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

A foundry will happily process a single wafer for you. The price won't be the same as when you run a thousand wafers a month, though.

Have you ever had a foundry run a single wafer for you?

They regularly run a single wafer from a mask set, but you might have a point. I don't actually know anyone who went to a foundry and only did one wafer of business with them.

[jmelson]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

Ok so that makes it 1000 * $1600  per wafer or USD 1.6M per month. But you also do get 15000 dies per wafer or 15000 * 1000 = 15M dies per month.
So per die cost is 15000/1600 that is around $0.11. Seems to be pretty good for a 10F.
But Microchip need to have assured sales right for it to be profitable?
Another issue for Microchip 15M chips per month is a lot, how will they sell that much, they may probably have another deal with the foundry?

But, DO NOT FORGET, your mask set costs you about $1 million - maybe even a lot more!

Jon

[jmelson]

They regularly run a single wafer from a mask set, but you might have a point. I don't actually know anyone who went to a foundry and only did one wafer of business with them.

I believe MOSIS typically runs about 3-5 wafers for their multi-project runs.  That is a bit of insurance against goofs at the foundry.  The cost of the extra wafers TOTALLY disappears compared to the cost of the masks.

Jon

[coppice]

Ok so that makes it 1000 * $1600  per wafer or USD 1.6M per month. But you also do get 15000 dies per wafer or 15000 * 1000 = 15M dies per month.
So per die cost is 15000/1600 that is around $0.11. Seems to be pretty good for a 10F.
But Microchip need to have assured sales right for it to be profitable?
Another issue for Microchip 15M chips per month is a lot, how will they sell that much, they may probably have another deal with the foundry?

But, DO NOT FORGET, your mask set costs you about $1 million - maybe even a lot more!

His figures are for a 350nm process. Masks for 350nm processes are not $1M.

[coppice]

They regularly run a single wafer from a mask set, but you might have a point. I don't actually know anyone who went to a foundry and only did one wafer of business with them.

I believe MOSIS typically runs about 3-5 wafers for their multi-project runs.  That is a bit of insurance against goofs at the foundry.  The cost of the extra wafers TOTALLY disappears compared to the cost of the masks.

Sure, it makes no rational sense to process just one wafer after spending a fortune to make a mask set. Back in the 80s, in the 2um era, direct e-beam written wafers were much saner as one offs.

[Wimberleytech]

To work with a foundry, you will have to commit to many thousands of wafers in production.

So did you have to commit for like 5000 wafers?

That is a detail I do not recall.  I would think at least 1000 wafers/month.  A foundry is in the speculation business.  They will make a bet on your viability.  If they believe in your business plan, they will be willing to do much smaller quantities while betting on the future large volumes.

A foundry will happily process a single wafer for you. The price won't be the same as when you run a thousand wafers a month, though.

Have you ever had a foundry run a single wafer for you?

They regularly run a single wafer from a mask set, but you might have a point. I don't actually know anyone who went to a foundry and only did one wafer of business with them.

A foundry (e.g., TSMC) will run a prototype lot (generally six wafers) with the expectation that it will turn into production after validation.  They have billions invested in the foundry.  They cannot run a single wafer here and there for somebody doing a science project.

[Wimberleytech]

Ok so that makes it 1000 * $1600  per wafer or USD 1.6M per month. But you also do get 15000 dies per wafer or 15000 * 1000 = 15M dies per month.
So per die cost is 15000/1600 that is around $0.11. Seems to be pretty good for a 10F.
But Microchip need to have assured sales right for it to be profitable?
Another issue for Microchip 15M chips per month is a lot, how will they sell that much, they may probably have another deal with the foundry?

But, DO NOT FORGET, your mask set costs you about $1 million - maybe even a lot more!

His figures are for a 350nm process. Masks for 350nm processes are not $1M.

Correct.  I think a mask set was on the order of $50K.
For a anything under 60nm, $1M may be close.

[brucehoult]

They regularly run a single wafer from a mask set, but you might have a point. I don't actually know anyone who went to a foundry and only did one wafer of business with them.

I believe MOSIS typically runs about 3-5 wafers for their multi-project runs.  That is a bit of insurance against goofs at the foundry.  The cost of the extra wafers TOTALLY disappears compared to the cost of the masks.

I've heard that there's no choice on multi-project runs as they are different size and shapes packed in and sawing up the wafer to extract some of the dice destroys other nearby ones. It's cheaper to pack them in and make multiple wafers than to align everything in rows and columns the size of the largest die in each row/column plus margin for the saw.

[jmelson]

Correct.  I think a mask set was on the order of $50K.
For a anything under 60nm, $1M may be close.

I assure you, TODAY, a CMOS mask set at 350 nm is going to be WAY more than $50K.  Maybe a simple, all-digital mask set might go for $200K, but for mixed-signal, there will be a bunch more layers, so it bumps up the price.  I think MOSIS has their masks done in the US, so that may affect the price.

Jon

[jmelson]

I've heard that there's no choice on multi-project runs as they are different size and shapes packed in and sawing up the wafer to extract some of the dice destroys other nearby ones. It's cheaper to pack them in and make multiple wafers than to align everything in rows and columns the size of the largest die in each row/column plus margin for the saw.

On educational projects at MOSIS, they have more restrictive rules.  For commercial MPW projects, you set the size of the chip.  They will often build it slightly larger, to accommodate the sawing operation, but charge you by YOUR specified dimensions.  But, all our chips came out about the size we specified.
They obviously have some special tricks they use in the sawing operation to make this work.

Jon

[Wimberleytech]

Correct.  I think a mask set was on the order of $50K.
For a anything under 60nm, $1M may be close.

I assure you, TODAY, a CMOS mask set at 350 nm is going to be WAY more than $50K.  Maybe a simple, all-digital mask set might go for $200K, but for mixed-signal, there will be a bunch more layers, so it bumps up the price.  I think MOSIS has their masks done in the US, so that may affect the price.

Jon

Well, I pulled out my notebook from 1999.  16 masks DPTM was $50K.  Addition for an extra metal layer.  Today??  Dunno.  Rather doubt your $200K number.  But I have some real-time connections...I will see.

[amyk]

Sure, it makes no rational sense to process just one wafer after spending a fortune to make a mask set. Back in the 80s, in the 2um era, direct e-beam written wafers were much saner as one offs.

https://en.wikipedia.org/wiki/Maskless_lithography

Interesting. I wonder if there are any companies that still offer prototyping on larger processes using direct-write, because from the discussion I gather the bulk of the $$$ in IC prototyping is in the mask (why masks are so expensive is the other question I'm curious about --- is there a ton of human labour involved, and/or do they take a very long time to make?)

[coppice]

Sure, it makes no rational sense to process just one wafer after spending a fortune to make a mask set. Back in the 80s, in the 2um era, direct e-beam written wafers were much saner as one offs.

https://en.wikipedia.org/wiki/Maskless_lithography

Interesting. I wonder if there are any companies that still offer prototyping on larger processes using direct-write, because from the discussion I gather the bulk of the $$$ in IC prototyping is in the mask (why masks are so expensive is the other question I'm curious about --- is there a ton of human labour involved, and/or do they take a very long time to make?)

The bulk of your external purchasing costs are software tools and mask costs. However, the bulk of the money you spend is on the engineering work itself. If you are worried about $100k to $200k for a mask set for a medium geometry process (350nm to 180nm), you certainly won't be able to afford to salary bill.

[Wimberleytech]

Here is some data from anysilicon.com (2016). 180nm is under $100k.

[Wimberleytech]

Interesting. I wonder if there are any companies that still offer prototyping on larger processes using direct-write, because from the discussion I gather the bulk of the $$$ in IC prototyping is in the mask (why masks are so expensive is the other question I'm curious about --- is there a ton of human labour involved, and/or do they take a very long time to make?)

Building a plant to produce fine-line masks can cost $100 million.  Then you have to run it and depreciate it.

[ZeroResistance]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Here is ballpark based on what a 0.35um flash silicided poly, 4 layers of metal, with cap poly and poly resistor options
Mask costs not included here.

Can you elaborate how you arrived to final cost of USD 0.68. is that the final cost of a packaged chip?
Also you have taken wafer cost as USD 1600 is that the cost of wafer for 0.35um process and for a quantitly of 1000 wafers / month. I mean the wafer cost would change right for a 0.18um process?

[ZeroResistance]

These are wafer cost's from year 2014




for 200mm 0.35u it shows as USD 460.

Taken from http://www.icinsights.com/news/bulletins/LeadingEdge-IC-Foundry-Market-Forecast-To-Increase-72-In-2014/

[Kjelt]

why masks are so expensive is the other question I'm curious about --- is there a ton of human labour involved, and/or do they take a very long time to make?)

I was curious about this to. AFAIK with modern low nm processes the costs for a reticle are in the specialized software and processing time to create the reticles.
It is no longer a simple question of " I want an unexposed square form on my wafer so the reticle has a square black shape on it 4 times bigger than on the wafer".
You need to take into account the UV laserlight which is absorbed by glass so you need special glass, phase shifts, lens deviations, abberations on the edge, reflections and I don't know what more. If you look at the finished reticle you don't recognize the original pattern but it is what you finally get on the wafer. There are lots and lots of raytracing and calculations needed, and ofcourse the accurate creation of the reticle, even 4 times bigger you still need 10's of nm accuracy on your pattern. IIRC it takes at least a month to create a complete reticle set.

Just an example of a company: http://www.photronics.com/plab/phase-shift-masks-eapsm/

[srce]

I've heard that there's no choice on multi-project runs as they are different size and shapes packed in and sawing up the wafer to extract some of the dice destroys other nearby ones. It's cheaper to pack them in and make multiple wafers than to align everything in rows and columns the size of the largest die in each row/column plus margin for the saw.

On educational projects at MOSIS, they have more restrictive rules.  For commercial MPW projects, you set the size of the chip.  They will often build it slightly larger, to accommodate the sawing operation, but charge you by YOUR specified dimensions.  But, all our chips came out about the size we specified.
They obviously have some special tricks they use in the sawing operation to make this work.

It depends on the foundry, but quite often, you pay per fixed block size, regardless of the size of your die. The block sizes specified by MOSIS and Europractice are just based on what the foundry offer, except that they sometimes they further subdivide them (E.g. Europractice's mini@sics).

[srce]

These are wafer cost's from year 2014




for 200mm 0.35u it shows as USD 460.

Taken from http://www.icinsights.com/news/bulletins/LeadingEdge-IC-Foundry-Market-Forecast-To-Increase-72-In-2014/

Here's the figures for this year



But you probably aren't going to see prices like that. 

[ZeroResistance]

But you probably aren't going to see prices like that. 

How much would you multiply the $ figures with to get a realistic value. And here I'm talking about regular foundry orders and not MPW.

[coppice]

Here's the figures for this year



But you probably aren't going to see prices like that. 

There are two issues to note with those prices:

• They are baseline prices for the simplest of logic wafers. If you are doing ultra low power, or mixed signal, or anything above minimal CMOS logic, there are more masks, more processing steps, and more cost.
• They are for customers with high run rates, and huge amounts of in house expertise, whose customer service costs are the lowest possible.

.

[ZeroResistance]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

[TheUnnamedNewbie]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

This depends on what you mean when you say 'lowest feature size'. I'd say a diode, since you pretty much form two diodes every time you make a MOS. In the CMOS technologies I have seen, the PMOS and NMOS device are the same size. The difference is that one of the two has to be placed in a well (usually the P-type device as we build on a p-substrate, so we first need to make an N-well). This makes the smallest possible isolated PMOS a bit bigger than the equivalent NMOS. But for analog design (and RF design even more so) we care mostly about the gate length, as that is one of the main factors in the electrical performance, and, in general, a shorter gate means a better transistor (but also a lower-voltage rated one - just a volt or less on the smallest of technologies).

[Kjelt]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

IIRC the conductivity of the P doping material (Boron i believe) is two to three times less than the N doping material (phosphor) which will result for the same current in a two to three time larger surface. This I guess is the reason the Power Fets these days are dominantly NFets ? 

[srce]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

[amyk]

and I guess what you mean by feature size

This is important to call out because transistors on a IC do not exist as discrete units; they're effectively formed from the interaction between the different layers. You can see that even with something like this 4004 which uses a very old process: http://alumni.media.mit.edu/~mcnerney/2009-4004/4004-masks-composite.jpg

[Jackson]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

IIRC the conductivity of the P doping material (Boron i believe) is two to three times less than the N doping material (phosphor) which will result for the same current in a two to three time larger surface. This I guess is the reason the Power Fets these days are dominantly NFets ? 

Correct - for Silicon, hole mobility is 2-3x lower than it is for electron mobility, hence the rule of thumb to size up your PMOS transistor width to get equivalent current flow. If you're dealing with non-Silicon processes it will be different.

[ZeroResistance]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?
The diode seems to be bigger than the PMOS and NMOS, that was supposed to be the smallest.
And what is PNP that looks quite big?

[Kjelt]

This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?

Yes for the SAME current, in this case they are probably just "digital signal" fets for logical gates that do not need to source much current.

[Kjelt]

Here is something to read, p14 and on

http://people.ee.duke.edu/~krish/teaching/Lectures/MOS.pdf

[srce]

So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?

They're the same size. The minimum gate size for both is the same: L=60nm, W=120nm (but note the total area of the transistor is much bigger than this!) However, if you were making an inverter, due to the difference in carrier mobility, you might choose to make the PMOS bigger, to get similar rise/fall times, but you don't have to.

The diode seems to be bigger than the PMOS and NMOS, that was supposed to be the smallest.

It depends what you're actually measuring and how "good" a diode you want.

And what is PNP that looks quite big?

It's a vertical PNP BJT. It's a CMOS process, so the BJTs aren't great. If BJTs are what you're interested in, you need to look at BiCMOS or Bipolar process.

[ZeroResistance]

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image?

[srce]

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image?

The major custom design package is Cadence Virtuoso. Also look at Synopsys Custom Compiler and Tanner AMS, which are less popular, but cheaper. What will really drive your selection will probably be what PDKs are available from the foundry you want to use, as they do not work with all tools.

Magic is just a layout tool, I believe, and you need to draw everything by hand. The above have schematic driven layout using parameterizable cells, auto-routing and realtime DRC and simulation environments, etc. They're expensive, but if you're serious  about IC design, then you'll need them.

[ZeroResistance]

That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image?

The major custom design package is Cadence Virtuoso. Also look at Synopsys Custom Compiler and Tanner AMS, which are less popular, but cheaper. What will really drive your selection will probably be what PDKs are available from the foundry you want to use, as they do not work with all tools.

Magic is just a layout tool, I believe, and you need to draw everything by hand. The above have schematic driven layout using parameterizable cells, auto-routing and realtime DRC and simulation environments, etc. They're expensive, but if you're serious  about IC design, then you'll need them.

ok! so did you place those components in Cadence Virtuoso?

[srce]

This is Virtuoso - this time for a 28nm process - showing an NMOS, PMOS and VPNP as both schematic and layout.

[ZeroResistance]

This is Virtuoso - this time for a 28nm process - showing an NMOS, PMOS and VPNP as both schematic and layout.

This is mind boggling! Many thanks again!
The PNP is gigantic.
The FETs in the symbols seem like JFET's so do they use JFET or MOSFET at the lowest level? I guess recently they have started with  FinFet's..

[amyk]

People have successfully used free tools like MAGIC to make ICs:

https://www.planetanalog.com/author.asp?section_id=526&doc_id=559519

There is analogy with PCB design, in that you can use a lot of different software but in the end the fab only needs the graphics for each layer, just like with PCB gerbers.

[srce]

The PNP is gigantic.

I'm not sure that 1um is gigantic 

The FETs in the symbols seem like JFET's so do they use JFET or MOSFET at the lowest level?

You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.

[ZeroResistance]

You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.

It's my mistake I got the symbols wrong.

Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
So is a transistor sized 80n x 30n for a 28nm process?

[srce]

Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?

m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)

So is a transistor sized 80n x 30n for a 28nm process?

ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).

[ZeroResistance]

Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?

m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)

So is a transistor sized 80n x 30n for a 28nm process?

ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).

What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

[Wimberleytech]

What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

This is what I call the unit matching principle.  It applies to MOS transistors, BJTs, resistors, capacitors, etc.

[srce]

What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?

Yep. But you'll notice the W is split between them. i.e. each finger has W' = W/n

Same would have been the case with m=2 right?.

No, you'd get two separate transistors each with W'=W. Also their drains would not be shared, so they'd have a larger total area.

There's a lot of other parameters to play with too (And then different transistor types too - different threshold voltages / oxide thickness etc - 36 different ones in this process!).

[ZeroResistance]

Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?

[Wimberleytech]

Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?

If you open your eyes only at midnight and at noon, the sun gives you two intensities (0 and 1).  If you keep your eyes open continuously, the sun's intensity gradually increases to its peak and then gradually decreases to its minimum.
The first case is digital while the second is analog--it is all a matter of your sample rate.

An inverter is a digital gate.  It outputs two logic levels: 0 and 1 ONLY IF you sample it such that you NEVER see the transitions from 0 to 1 and 1 to 0.  During those transitions, one can say that the signal is analog.

The IEEE dictionary defines analog as "continuous" whereas digital is "discrete" (my paraphrase).  If you look close enough...everything is analog (everything above quantum level, that is).

[coppice]

Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?

You say "saturation mode" like its a clean digital state, when in fact its just as analogue as the linear region. How hard you push things into saturation affects how much energy gets stored, and has to be removed to get the thing out of saturation. For high digital performance, saturation has to be well controlled. Unless you get down to something which functions by a single molecular flip, I don't see how anything being used for digital purposes at the macro level is not built on an underlying analogue scheme.

[srce]

It's all analog until you get to the quantum level. Then it turns out everything is digital. 

[Wimberleytech]

Just a little cleanup...
For MOSFETs, Saturation is the state where Vds > Vgs - VT and Linear when Vds < Vgs - VT
When an MOS transistor is strongly on and Vds is near zero, it is operating in the Linear region, not Saturation region.
For CMOS logic gates, transistors spend precious little time in the Saturation region.

[TheUnnamedNewbie]

What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.

Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
 
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.



If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).


*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.

[ZeroResistance]

What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.

Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
 
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.



If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).


*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.

Thanks for sharing.
This is amazing and just goes to show the intricacies associated with chip design?
I guess all this came from your experience in chip design.
Is there a reference or book that would illustrate these practices, that one can read before diving into chip design?

[ZeroResistance]

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
That means the gate would also be porportionately longer?

EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.

Yes its still not clear each layer seems to have finger shaped projections, so its not clear what is drain, gate or source.
I guess the solid block at the bottom is the substrate?

[Richard Crowley]

So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?

Please refer to the image in response # 127.
If you look at the schematic diagram on the left, you will see that the notation says:

w=160n
l = 30n

That means that the gate LENGTH is 30n and the WIDTH is 160n

And if you look at the layout on the right side, the LENGTH is the distance between the Source and the Drain.  And the WIDTH is the orthogonal measurement.  You can eyeball that the WIDTH is about 5x the LENGTH distance.

The first layout shows a simple transistor.  The second layout shows a transistor implemented in two sections ("n=2") where the total width is the same (160n), but it is broken up into two equal (80n) parts.

its not clear what is drain, gate or source.

If you look closely at the layout (right side) of the image in #127, the Source is labeled with "/s/" and the Drain with "/d/" and the Gate with "/g/"

I guess the solid block at the bottom is the substrate?

Yes.

[TheUnnamedNewbie]

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
That means the gate would also be porportionately longer?

The origin of 'width' and 'length' comes from considering the charge carriers that move. They go from source to drain. The 'length' is the distance they have to travel from one to the other. The width is how 'wide' (from the charge carriers view as it is traveling from source to drain) the channel is.

EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.

Yes its still not clear each layer seems to have finger shaped projections, so its not clear what is drain, gate or source.
I guess the solid block at the bottom is the substrate?

The network you can see is only for the gate or the drain (source would be connected to the substrate, the solid block). You would have two of these, coming in from both sides (so one would look like the one in the picture, the other would be mirrored) to connect both.

[ZeroResistance]

So, how many layers would a typical chip have, what defines the number of layers?
Do more layers cause any side effects on the design, like increased capacitance etc.

[TheUnnamedNewbie]

In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)

[ZeroResistance]

In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.

[Wimberleytech]

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.

Transistors are always the bottom layers.  You need at least one layer of metal for ohmic contact to transistor terminals.

[TheUnnamedNewbie]

Transistors are formed in the front-end-of-line, which is where are the high temperature steps are done (for doping and forming the wells). Depending on the technology, you might have a metal or a poly-si gate. After that, you start counting metal layers (which would be the back-end-of-line, or BEOL)

[srce]

In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.

Nope. The standard terminology is that "layers" usually means "metal layers" and this is just the number of metal layers you have for routing. It doesn't have anything to do with transistors or number of masks, which will be a lot more.

For example, take this http://www.europractice-ic.com/technologies_TSMC.php TSMC .18 process. Number of metal layers can be from 3 to 6, so you'll often hear this be called a 6 metal layer process.

However, the number of masks is given as between 26 and 31. You need one mask for each metal layer + a mask for the vias inbetween the metal layers. Then most of the other masks are basically to make the transistors.

[Kjelt]

In laymens terms you have a few to tens of nm structures on the bottom but you need to :

- connect the G,S,D to power and other logical elements
- connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large.
So in the metal layers you do the routing but also in steps scaling up from nm to um structures.
That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching.

[TheUnnamedNewbie]

There are these two classic images by, if I'm not mistaken, intel and IBM:

Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers):


IBM. In this one you can see the fins (this is a prototype 10 nm fin-fet process) of the transistors at the bottom):


Also notice how, esp on the lower layers, the metals have a very repeatable pattern. A lot of these thin metals might not actually be connected, but they are added because it gives a more repeatable and constant profile, and gives better results in the CMP process.

Here is another nice image to show you just how big a scale difference there is between these layers. The red tiny things at the bottom would be the poly of the gates (under the blue layers). Big pink bottom is the substrate. (this image is the connection to a differential pair for a oscillator). Tha transistors would be under neath all of this mess, under the dark blue lines (where the tiny red bits pop out). Source: Wouter Steyaert, THz electronics in nanometer CMOS. PDF: https://core.ac.uk/download/pdf/84932070.pdf

[ZeroResistance]

In laymens terms you have a few to tens of nm structures on the bottom but you need to :

- connect the G,S,D to power and other logical elements
- connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large.
So in the metal layers you do the routing but also in steps scaling up from nm to um structures.
That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching.

I got the G, S, D part.
but what are end pads? and why do you scale up from nm to um as you move top the layers?

[Richard Crowley]

I got the G, S, D part.
but what are end pads? and why do you scale up from nm to um as you move top the layers?

Simply so that they are large enough to actually make a connection into the Real World.
Contact pads that seem as large as an aircraft carrier (when viewed from the perspective where you can "see" individual transistors) are barely visible in the Real World unless viewing through a microscope.

We once printed out the die layout of a CPU chip (386 IIRC) so that it was 30 feet across.  The bond pads were something around 4 inches 100mm square and the plot filled one wing of the cafeteria.  But even at that resolution, the individual transistors weren't really visible. They were only 2-3 pixels in size.

[ZeroResistance]

There are these two classic images by, if I'm not mistaken, intel and IBM:

Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers): ...

This is mind bogglingly amazing!!
How on earth do you get such great images?!

Interesting thing that you talk about the repeatable pattern. And there also seems to be a pattern on the upper half of the thick substrate layer (the bottommost one).
What patterns are those?
Are the substrate and the 2 layers above it, the transistors?

With regards to the bottom most image what kind of program generates such kind of design, is it a CAD program or a specialized IC design software?

Also, when do you use polysilicon and when do you use metal, I guess both thes are used for interconnects right?

[TheUnnamedNewbie]

There are these two classic images by, if I'm not mistaken, intel and IBM:

Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers): ...

This is mind bogglingly amazing!!
How on earth do you get such great images?!

Interesting thing that you talk about the repeatable pattern. And there also seems to be a pattern on the upper half of the thick substrate layer (the bottommost one).
What patterns are those?
Are the substrate and the 2 layers above it, the transistors?

The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):



This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).

Fin-Fets, which is what you see in the second picture, involves growing fins. It's these fins I think you are talking about.

No metals are involved in making the actual transistors, they are only used after the transistors are made, to connect them to each other (exception would be metal-gate, but again, details that are not important now).

With regards to the bottom most image what kind of program generates such kind of design, is it a CAD program or a specialized IC design software?

When we design such a thing we use a combination of tools: Cadence Layout (G)XL (to do the actual drawing of materials), Keysight EEsof ADS/momentum (first, fast simulations of simpler structures), Ansys HFSS (detailed high-performance analysis of EM stuff), Mentor Calibre (Layout-vs-schematic and parasitic-extraction, though the latter isn't that usefull anymore to us, since we simulate with EM simulators).  It is all hand-drawn, there isn't some auto-generator for it.

To get the nice 3D plot: I believe the university of Twente has a nice 3D GDSII viewer, which is often used for that. Mind you, apart from making nice images for publications and such we don't tend to use it much.

[ZeroResistance]

Fin-Fets, which is what you see in the second picture, involves growing fins. It's these fins I think you are talking about.

Is the second picture in the link you provided because I don't see it in the post?

[ZeroResistance]

The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):



This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).

1. For NMOS why make a p-Si well when a P-Si already exists?
2. What is punch stop?
3. What is STI?
4. The silicide layers are used as conductors? But then why the gate has n+poly also where as the drain and source has only silicide and no n+ poly?

I guess I'll do some searches on the internet and see what answer each of those questions return?

[Wimberleytech]

The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):



This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).



1. For NMOS why make a p-Si well when a P-Si already exists?

The main reason is that the doping profile of each well can be individually tailored.  Also provides isolation benefits

2. What is punch stop?

Not sure

3. What is STI?

Shallow Trench Isolation 
This technique replaces  the old LOCOS technique

4. The silicide layers are used as conductors? But then why the gate has n+poly also where as the drain and source has only silicide and no n+ poly?

Yes, silicide is a refractory metal--a conductor.
Polysilicon is the preferred material to make defect-free gates.  Metal is terrible as the gate-oxide interface
There is no need for poly at the source and drains.

[ZeroResistance]

Just a few questions that come to my mind while contemplating on the topic

1. Why is the silicon wafer when its being manufactured from a liquid kind of state not 100% pure silicon?. Why is it doped to become an N type or a P Type substrate? I mean some dopants are added to the mix when the wafer is being manufactured?

2. Why is an epitaxial coating done over the silicon wafer before any other processes are done?

3. Is there a comprehensive list of steps for silicon chip  fabrication?

TIA

[Wimberleytech]

Just a few questions that come to my mind while contemplating on the topic

1. Why is the silicon wafer when its being manufactured from a liquid kind of state not 100% pure silicon?. Why is it doped to become an N type or a P Type substrate? I mean some dopants are added to the mix when the wafer is being manufactured?

This is a deep and involved topic with lots of history. 
Lets work backwords from the transistor structure.
An N-channel transistor needs N+ source and drain (the "+" indicates heavy doping of donor atoms) diffused into silicon doped with acceptor atoms so that the underlying material is doped P type.  In order to achieve desired transistor performance, that material is very lightly doped...we call it P- where the "minus" means lightly doped.  In the above, Phosphorous is typically used as a donor dopant, and Boron is used as an acceptor dopant.

If all you wanted to build were N-channel transistors, you could manufacture a silicon wafer that has a P- doping.  In fact, early MOS technology was either totally N-channel, or totally P-channel.  Of course, for a totally P-channel circuit, the wafer would have to be manufactured with N- doping.

Wafers come from silicon ingots, or boules, that are manufactured using the Czochralski method.  Molten silicon is gradually extracted starting with a crystalline seed.  For doping requirements, the molten silicon can be doped with donors or acceptors to achieve the desired doping.

Nobody uses NMOS, or PMOS any more.  CMOS instead!!  So, how do you put a p-channel transistor in a wafer that is already doped P- ?? 

Well, you have to create regions on the wafer that are lightly doped N-.  These regions are called "wells."  So, for CMOS, you may start with a lightly doped P- wafer as the basic substrate, then create well that is doped N- (either by ion implantation, or diffusion, or combination of both).  Withing the n-well, you can put p-channel transistors.  In the regions outside of the well, you can put the n-channel transtors.  Now you have CMOS!! 

That is pretty much it, except for about a million other details.

2. Why is an epitaxial coating done over the silicon wafer before any other processes are done?

Epi layers can be created with more precise and tuned properties than can be achieved with the C-growth method.  The underlying substrate can be high conductivity enabling better performance under certain condition.

3. Is there a comprehensive list of steps for silicon chip  fabrication?

Yes.  Have you googled for this?
Also, the processing steps of changed over the years-- metal-gate, silicon-gate, oxide-isolated, shallow-tranch isolation, on and on...

Go here: https://aicdesign.org/wp-content/uploads/2018/08/lecture02-131209.pdf

[Richard Crowley]

3. Is there a comprehensive list of steps for silicon chip  fabrication?

https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#List_of_steps

That is as good as you are going to get if you are asking for a list of generic types of processes.

If you are asking about the exact steps for a particular device or fab process, that is typically a closely-held secret.

[ZeroResistance]

An N-channel transistor needs N+ source and drain (the "+" indicates heavy doping of donor atoms) diffused into silicon doped with acceptor atoms so that the underlying material is doped P type.  In order to achieve desired transistor performance, that material is very lightly doped...we call it P- where the "minus" means lightly doped.  In the above, Phosphorous is typically used as a donor dopant, and Boron is used as an acceptor dopant.

The "diffused" term that you use here what does that do? I heard that ion implantation is used to for adding impurities (doping) to the silicon wafer. What does diffusion do?

Secondly you refer to the wafer being lightly doped either N- or P-.
Is that it because from what I had read so far is that the subtrate is heavily doped P+ or N+ and on top of this there is a lightly doped epitaxial layer grows P- or N-.

[Wimberleytech]

An N-channel transistor needs N+ source and drain (the "+" indicates heavy doping of donor atoms) diffused into silicon doped with acceptor atoms so that the underlying material is doped P type.  In order to achieve desired transistor performance, that material is very lightly doped...we call it P- where the "minus" means lightly doped.  In the above, Phosphorous is typically used as a donor dopant, and Boron is used as an acceptor dopant.

The "diffused" term that you use here what does that do? I heard that ion implantation is used to for adding impurities (doping) to the silicon wafer. What does diffusion do?

Secondly you refer to the wafer being lightly doped either N- or P-.
Is that it because from what I had read so far is that the subtrate is heavily doped P+ or N+ and on top of this there is a lightly doped epitaxial layer grows P- or N-.

In the early days, diffusion was the method for creating the heavily doped drains and sources.  Yes, in modern times, it is done using ion implantation.

In modern processes, the substrate is heavily doped.  So in order to make a good transistor, a lightly doped region is required...so an epitaxial layer that is very lightly doped is deposited on top of the heavily doped substrate.  All modern processes use twin wells--one well doped P- and the other doped N-.  These wells sit inside (on top of) the epitaxial layer.

[ZeroResistance]

What about Maskless Lithography systems or Direct Write systems like Mapper https://mapper.nl/.
The say that it does patterning without a mask.
So does this system only replaced the mask?
Because transistor fabrication would still need Diffusion / Ion Implanting and other processes involved in chip fabrication? How does Mapper achieve that?
Would additional equipment be needed in addition to Mapper?

TIA

[Wimberleytech]

What about Maskless Lithography systems or Direct Write systems like Mapper https://mapper.nl/.
The say that it does patterning without a mask.
So does this system only replaced the mask?
Because transistor fabrication would still need Diffusion / Ion Implanting and other processes involved in chip fabrication? How does Mapper achieve that?
Would additional equipment be needed in addition to Mapper?

TIA

Direct-write systems suffer from throughput and throughput is EVERYTHING (well...mostly everything).
Transistor fab still needs ion implanting and the other processes.  Direct Write is just a substitute for masks.

Mapper looks interesting...will have to study that more to see if it is a breakthrough.

[coppice]

What about Maskless Lithography systems or Direct Write systems like Mapper https://mapper.nl/.
The say that it does patterning without a mask.
So does this system only replaced the mask?
Because transistor fabrication would still need Diffusion / Ion Implanting and other processes involved in chip fabrication? How does Mapper achieve that?
Would additional equipment be needed in addition to Mapper?

In the 1980s, when 1um to 2um geometries were the state of the art, direct e-beam machines were used in a number of places for prototyping, mostly because they eliminated the mask production step. They had limited effectiveness, though. They aren't suitable for mass production, because they are so slow, so if a prototype works well, a mask set is needed for production. The mask process is different, so when the masked parts are produced the design has to be requalified, especially the analogue sections, and fast digital paths. So, direct e-beam was mostly useful for checking out logic designs quickly. These days people mostly use FPGAs to check out logic, which could be why most direct e-beam services have disappeared.

It seems Mapper is trying to make direct e-beam fast, by using a huge number of concurrent beams, so a successful prototype can be directly turned into volume production parts. It would certainly mean a lot more bugs requiring an all layers revision (ALR), would be fixed than is the case today. The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

[Wimberleytech]

...The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

Spare gates!   

Requal still needed though.

[coppice]

...The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

Spare gates!   

Requal still needed though.

Everyone adds spare gates these days, and they do reduce the number of ALRs considerably. They are seldom able to fix more than simple logic errors, though.

[Wimberleytech]

...The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

Spare gates!   

Requal still needed though.

Everyone adds spare gates these days, and they do reduce the number of ALRs considerably. They are seldom able to fix more than simple logic errors, though.

Yes, indeed.
Spare analog can save an ALR from time to time as well.
Another useful feature is spare metal runs...wonder why???

[coppice]

...The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

Spare gates!   

Requal still needed though.

Everyone adds spare gates these days, and they do reduce the number of ALRs considerably. They are seldom able to fix more than simple logic errors, though.

Yes, indeed.
Spare analog can save an ALR from time to time as well.
Another useful feature is spare metal runs...wonder why???

I wonder what the overall ratio of metal fixes to ALRs is, across the semiconductor industry?

These days even a single layer fix is getting so expensive, it can be hard to get managers to commit to them.

[Wimberleytech]

...The cost of masks, and the time to requalify, is a huge deterrent to fixing things right now.

Spare gates!   

Requal still needed though.

Everyone adds spare gates these days, and they do reduce the number of ALRs considerably. They are seldom able to fix more than simple logic errors, though.

Yes, indeed.
Spare analog can save an ALR from time to time as well.
Another useful feature is spare metal runs...wonder why???

I wonder what the overall ratio of metal fixes to ALRs is, across the semiconductor industry?

These days even a single layer fix is getting so expensive, it can be hard to get managers to commit to them.

Good question.  My last node was 180nm, so I have been out of the industry for awhile.
At my last company (which I started), I dont think we ever did an ALR--maybe one.  That was out of about a dozen base platforms.  Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time.  Now, doing RF or extreme precision...perhaps another story.

[coppice]

I wonder what the overall ratio of metal fixes to ALRs is, across the semiconductor industry?

These days even a single layer fix is getting so expensive, it can be hard to get managers to commit to them.

Good question.  My last node was 180nm, so I have been out of the industry for awhile.
At my last company (which I started), I dont think we ever did an ALR--maybe one.  That was out of about a dozen base platforms.  Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time.  Now, doing RF or extreme precision...perhaps another story.

When you find an obscure but important bug in something like the brownout module, or other hybrid analogue/digital part, of something like an MCU, it usually isn't fixable by metal changes, and by the time you find it there might be several mask sets with that issue. Fun times for ALR bills.

[brucehoult]

At my last company (which I started), I dont think we ever did an ALR--maybe one.  That was out of about a dozen base platforms.  Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time.  Now, doing RF or extreme precision...perhaps another story.

I agree with this. Maybe some analogish problem, but there's not much excuse for bad digital design now, especially if you don't overly complicate the design with seldom-used features.

At SiFive we use "agile hardware design". You can see Dave Paterson talking about it here

You can test fundamentals in tools such as Verilator, but pretty quickly you want to get into an FPGA where you can run at 50 MHz or 100 MHz and boot up Linux, build and test any software you want, even run SPEC in a week. You should be able to exercise the design enough that when it gets moved into an ASIC there are no show-stoppers.

[Wimberleytech]

At my last company (which I started), I dont think we ever did an ALR--maybe one.  That was out of about a dozen base platforms.  Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time.  Now, doing RF or extreme precision...perhaps another story.

I agree with this. Maybe some analogish problem, but there's not much excuse for bad digital design now, especially if you don't overly complicate the design with seldom-used features.

At SiFive we use "agile hardware design". You can see Dave Paterson talking about it here

You can test fundamentals in tools such as Verilator, but pretty quickly you want to get into an FPGA where you can run at 50 MHz or 100 MHz and boot up Linux, build and test any software you want, even run SPEC in a week. You should be able to exercise the design enough that when it gets moved into an ASIC there are no show-stoppers.

I had my team synthesize all of the digital to FPGA back in 1999.  We were certain of the logic.  When pushing speed, a little different story.

You cannot do a lot with analog spares, but there was one occasion where a designer was expecting a low-side bias current but the verilog model (which drove the hookup) had high-side bias.  Obviously did not work.  Solution?  I had designed an analog spare block that allowed for an easy turn-around mirror.  Saved an all-layer rev. plus it was quick...and on VC money, time is everything.

[ZeroResistance]

I had my team synthesize all of the digital to FPGA back in 1999.  We were certain of the logic.  When pushing speed, a little different story.

You cannot do a lot with analog spares, but there was one occasion where a designer was expecting a low-side bias current but the verilog model (which drove the hookup) had high-side bias.  Obviously did not work.  Solution?  I had designed an analog spare block that allowed for an easy turn-around mirror.  Saved an all-layer rev. plus it was quick...and on VC money, time is everything.

1. This sounds interesting. How does one make a one size fits all spare block. Because in the end anything could go wrong or have a bug.
2. Was this bug discovered after the masks were made?
3. Did you have to redo some masks after correcting this?

[Wimberleytech]

1. This sounds interesting. How does one make a one size fits all spare block. Because in the end anything could go wrong or have a bug.

You don't.  Just do the best you can.  Build transistor arrays, P, and N.  Make them long channel, cascoding ability.  Scale them so that you can mirror up or down. I cannot recall what else I used.

2. Was this bug discovered after the masks were made?

Discovered when power was applied to first prototype units!  Because I had run copious extra "spare metal" it was an easy FIB to fix and verify.

3. Did you have to redo some masks after correcting this?

Yes.  Metal mask only.  Went to production using the spare analog cells.

[coppice]

it was an easy FIB to fix and verify.

Easy and FIB is a combination of words I don't often see.

[Wimberleytech]

it was an easy FIB to fix and verify.

Easy and FIB is a combination of words I don't often see.

True...some are harder than others, but this one was easy. 
This was a 0.35um 2P5M embedded flash process, so pretty "fat" compared to what you see today.

[ZeroResistance]

What would be the accuracy of steppers / scanners, would it be something like +/- 500 pico meter.
Lets say for a 90nm technology node.