Author Topic: Chip making process  (Read 4528 times)

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Online srce

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Re: Chip making process
« Reply #125 on: October 19, 2018, 11:39:35 pm »
The PNP is gigantic.
I'm not sure that 1um is gigantic  :P
The FETs in the symbols seem like JFET's so do they use JFET or MOSFET at the lowest level?
You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.
 

Offline ZeroResistance

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Re: Chip making process
« Reply #126 on: October 19, 2018, 11:52:59 pm »
You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.
It's my mistake I got the symbols wrong.

Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
So is a transistor sized 80n x 30n for a 28nm process?
 

Online srce

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Re: Chip making process
« Reply #127 on: October 20, 2018, 12:17:29 am »
Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)

So is a transistor sized 80n x 30n for a 28nm process?
ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).





 

Offline ZeroResistance

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Re: Chip making process
« Reply #128 on: October 20, 2018, 12:41:03 am »
Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)

So is a transistor sized 80n x 30n for a 28nm process?
ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?
 

Offline Wimberleytech

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Re: Chip making process
« Reply #129 on: October 20, 2018, 01:21:20 am »

Quote
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.

This is what I call the unit matching principle.  It applies to MOS transistors, BJTs, resistors, capacitors, etc.
 
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Online srce

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Re: Chip making process
« Reply #130 on: October 20, 2018, 02:33:01 am »
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Yep. But you'll notice the W is split between them. i.e. each finger has W' = W/n
Same would have been the case with m=2 right?.
No, you'd get two separate transistors each with W'=W. Also their drains would not be shared, so they'd have a larger total area.

There's a lot of other parameters to play with too :P (And then different transistor types too - different threshold voltages / oxide thickness etc - 36 different ones in this process!).
« Last Edit: October 20, 2018, 02:43:23 am by srce »
 
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Offline ZeroResistance

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Re: Chip making process
« Reply #131 on: October 20, 2018, 08:11:13 pm »
Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?
 

Offline Wimberleytech

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Re: Chip making process
« Reply #132 on: October 20, 2018, 11:22:51 pm »
Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?

If you open your eyes only at midnight and at noon, the sun gives you two intensities (0 and 1).  If you keep your eyes open continuously, the sun's intensity gradually increases to its peak and then gradually decreases to its minimum.
The first case is digital while the second is analog--it is all a matter of your sample rate.

An inverter is a digital gate.  It outputs two logic levels: 0 and 1 ONLY IF you sample it such that you NEVER see the transitions from 0 to 1 and 1 to 0.  During those transitions, one can say that the signal is analog.

The IEEE dictionary defines analog as "continuous" whereas digital is "discrete" (my paraphrase).  If you look close enough...everything is analog (everything above quantum level, that is).
 
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Offline coppice

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Re: Chip making process
« Reply #133 on: October 20, 2018, 11:40:59 pm »
Still trying to wrap my head around
"At the lowest level everything is analog"

And how so? I guess you can use a transistor either in saturation mode or in linear mode. So should'nt it boil down to the operating mode of the tranistor?
You say "saturation mode" like its a clean digital state, when in fact its just as analogue as the linear region. How hard you push things into saturation affects how much energy gets stored, and has to be removed to get the thing out of saturation. For high digital performance, saturation has to be well controlled. Unless you get down to something which functions by a single molecular flip, I don't see how anything being used for digital purposes at the macro level is not built on an underlying analogue scheme.
 
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Online srce

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Re: Chip making process
« Reply #134 on: October 21, 2018, 04:43:49 am »
It's all analog until you get to the quantum level. Then it turns out everything is digital.  :P
 
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Offline Wimberleytech

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Re: Chip making process
« Reply #135 on: October 21, 2018, 04:59:58 am »
Just a little cleanup...
For MOSFETs, Saturation is the state where Vds > Vgs - VT and Linear when Vds < Vgs - VT
When an MOS transistor is strongly on and Vds is near zero, it is operating in the Linear region, not Saturation region.
For CMOS logic gates, transistors spend precious little time in the Saturation region.
 

Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #136 on: October 21, 2018, 05:15:49 pm »

Quote
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.


Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.

Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
 
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.



If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).


*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.
« Last Edit: October 21, 2018, 05:19:40 pm by TheUnnamedNewbie »
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Offline ZeroResistance

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Re: Chip making process
« Reply #137 on: October 21, 2018, 07:06:22 pm »

Quote
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?

The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.


Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.

Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
 
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.



If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).


*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.

Thanks for sharing.
This is amazing and just goes to show the intricacies associated with chip design?
I guess all this came from your experience in chip design.
Is there a reference or book that would illustrate these practices, that one can read before diving into chip design?
 

Offline ZeroResistance

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Re: Chip making process
« Reply #138 on: October 21, 2018, 07:33:56 pm »
The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.
So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
That means the gate would also be porportionately longer?

Quote
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.
Yes its still not clear each layer seems to have finger shaped projections, so its not clear what is drain, gate or source.
I guess the solid block at the bottom is the substrate?
 

Offline Richard Crowley

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Re: Chip making process
« Reply #139 on: October 21, 2018, 07:44:12 pm »
So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
Please refer to the image in response # 127.
If you look at the schematic diagram on the left, you will see that the notation says:

w=160n
l = 30n

That means that the gate LENGTH is 30n and the WIDTH is 160n

And if you look at the layout on the right side, the LENGTH is the distance between the Source and the Drain.  And the WIDTH is the orthogonal measurement.  You can eyeball that the WIDTH is about 5x the LENGTH distance.

The first layout shows a simple transistor.  The second layout shows a transistor implemented in two sections ("n=2") where the total width is the same (160n), but it is broken up into two equal (80n) parts.

Quote
its not clear what is drain, gate or source.
If you look closely at the layout (right side) of the image in #127, the Source is labeled with "/s/" and the Drain with "/d/" and the Gate with "/g/"
Quote
I guess the solid block at the bottom is the substrate?
Yes.
« Last Edit: October 21, 2018, 08:02:41 pm by Richard Crowley »
 
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Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #140 on: October 21, 2018, 08:09:36 pm »
The purpose for building a transistor out of several transistors in parallel is for matching.  If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor.  This achieves better matching than simply building the 2x transistor 2x wider.
So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
That means the gate would also be porportionately longer?

The origin of 'width' and 'length' comes from considering the charge carriers that move. They go from source to drain. The 'length' is the distance they have to travel from one to the other. The width is how 'wide' (from the charge carriers view as it is traveling from source to drain) the channel is.

EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.
Yes its still not clear each layer seems to have finger shaped projections, so its not clear what is drain, gate or source.
I guess the solid block at the bottom is the substrate?

The network you can see is only for the gate or the drain (source would be connected to the substrate, the solid block). You would have two of these, coming in from both sides (so one would look like the one in the picture, the other would be mirrored) to connect both.
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Offline ZeroResistance

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Re: Chip making process
« Reply #141 on: October 28, 2018, 04:45:24 am »
So, how many layers would a typical chip have, what defines the number of layers?
Do more layers cause any side effects on the design, like increased capacitance etc.
 

Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #142 on: October 28, 2018, 05:20:34 am »
In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)
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Offline ZeroResistance

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Re: Chip making process
« Reply #143 on: October 28, 2018, 05:35:18 am »
In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.
 

Offline Wimberleytech

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Re: Chip making process
« Reply #144 on: October 28, 2018, 05:38:00 am »
Quote

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.

Transistors are always the bottom layers.  You need at least one layer of metal for ohmic contact to transistor terminals.
 
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Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #145 on: October 28, 2018, 05:39:45 am »
Transistors are formed in the front-end-of-line, which is where are the high temperature steps are done (for doping and forming the wells). Depending on the technology, you might have a metal or a poly-si gate. After that, you start counting metal layers (which would be the back-end-of-line, or BEOL)
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Online srce

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Re: Chip making process
« Reply #146 on: October 28, 2018, 07:23:23 am »
In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with)

Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned.

Nope. The standard terminology is that "layers" usually means "metal layers" and this is just the number of metal layers you have for routing. It doesn't have anything to do with transistors or number of masks, which will be a lot more.

For example, take this http://www.europractice-ic.com/technologies_TSMC.php TSMC .18 process. Number of metal layers can be from 3 to 6, so you'll often hear this be called a 6 metal layer process.

However, the number of masks is given as between 26 and 31. You need one mask for each metal layer + a mask for the vias inbetween the metal layers. Then most of the other masks are basically to make the transistors.

« Last Edit: October 28, 2018, 07:24:55 am by srce »
 
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Online Kjelt

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Re: Chip making process
« Reply #147 on: October 28, 2018, 09:18:36 pm »
In laymens terms you have a few to tens of nm structures on the bottom but you need to :

- connect the G,S,D to power and other logical elements
- connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large.
So in the metal layers you do the routing but also in steps scaling up from nm to um structures.
That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching.
 
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Offline TheUnnamedNewbie

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Re: Chip making process
« Reply #148 on: October 28, 2018, 10:06:27 pm »
There are these two classic images by, if I'm not mistaken, intel and IBM:

Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers):


IBM. In this one you can see the fins (this is a prototype 10 nm fin-fet process) of the transistors at the bottom):


Also notice how, esp on the lower layers, the metals have a very repeatable pattern. A lot of these thin metals might not actually be connected, but they are added because it gives a more repeatable and constant profile, and gives better results in the CMP process.

Here is another nice image to show you just how big a scale difference there is between these layers. The red tiny things at the bottom would be the poly of the gates (under the blue layers). Big pink bottom is the substrate. (this image is the connection to a differential pair for a oscillator). Tha transistors would be under neath all of this mess, under the dark blue lines (where the tiny red bits pop out). Source: Wouter Steyaert, THz electronics in nanometer CMOS. PDF: https://core.ac.uk/download/pdf/84932070.pdf

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Offline ZeroResistance

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Re: Chip making process
« Reply #149 on: October 29, 2018, 12:29:10 am »
In laymens terms you have a few to tens of nm structures on the bottom but you need to :

- connect the G,S,D to power and other logical elements
- connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large.
So in the metal layers you do the routing but also in steps scaling up from nm to um structures.
That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching.

I got the G, S, D part.
but what are end pads? and why do you scale up from nm to um as you move top the layers?
 


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