Clock lower and upper bounds

[electr_peter]

Hello, EEVblog forum members,

I am interested in lower and upper bounds of clock frequency. I searched EEVblog forum, but I didn't find the answer to my question.
I am a beginner with electronics and MCUs. I read that each MCU/FPGA/interface protocol has clock frequency specifications. Typically, maximum or exact operating frequency (for serial protocols) is defined.

My understanding is that you cannot increase clock frequency above upper bound (at least by a much) - device would lose/miss clock. On the other hand, it seems that clock freq can be as low as you want - 1Hz, 0.1Hz, ... (as long as it has steep enough edges). You can even manipulate clock by hand.

My questions for forum users:
1) Can very slow clock be damaging to MCU/FPGA or other devices? Could too slow clock "burn in" wrong state or bit in MCU/FPGA or make it reset?
2) Are there silicon devices which do not work with too low frequency? I wouldn't count RF devices.

I appreciate your answers.

[ve7xen]

1) Can very slow clock be damaging to MCU/FPGA or other devices? Could too slow clock "burn in" wrong state or bit in MCU/FPGA or make it reset?

A clock with a very slow edge (ie. very long rise time) might cause some bad internal states to persist long enough to cause problems. I doubt permanent damage, but probably weirdness will occur.

2) Are there silicon devices which do not work with too low frequency? I wouldn't count RF devices.

Assuming you're just referring to logic here, then yes. There are two general classes of logic, static and dynamic. Static logic will work at any clock rate (assuming hold times etc. are all obeyed), as the combinatorial logic acts directly on the inputs to produce the outputs. By contrast dynamic logic requires a clock signal to drive the internal logic such that the outputs are refreshed. It's somewhat akin to the idea of 'dynamic RAM' which needs a refresh clock to refresh the internal cells frequently enough that they don't decay.

Dynamic logic isn't all that common in modern "slow" logic (modern microcontrollers etc.), though probably appears in high speed CPUs and the like. I believe FPGAs are purely static.

I appreciate your answers.
[/quote]

[electr_peter]

1) Can very slow clock be damaging to MCU/FPGA or other devices? Could too slow clock "burn in" wrong state or bit in MCU/FPGA or make it reset?

A clock with a very slow edge (ie. very long rise time) might cause some bad internal states to persist long enough to cause problems. I doubt permanent damage, but probably weirdness will occur.

2) Are there silicon devices which do not work with too low frequency? I wouldn't count RF devices.

Assuming you're just referring to logic here, then yes. There are two general classes of logic, static and dynamic. Static logic will work at any clock rate (assuming hold times etc. are all obeyed), as the combinatorial logic acts directly on the inputs to produce the outputs. By contrast dynamic logic requires a clock signal to drive the internal logic such that the outputs are refreshed. It's somewhat akin to the idea of 'dynamic RAM' which needs a refresh clock to refresh the internal cells frequently enough that they don't decay.

Thanks, ve7xen, I have not read about static/dynamic logic before. Discharge of capacitors explains why some devices need fast clock at all times to be able to operate.
Link to "Dynamic logic" in Wikipedia:

Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.

Static logic has no minimum clock rate—the clock can be paused indefinitely.

[T3sl4co1l]

Static logic should also not depend on the rate of change either, so beware: even apparently static designs may have dynamic elements in them.  Point being, I believe I have read a few datasheets which state that the clock frequency shouldn't be removed or changed suddenly, but gradual over some rate.

Chips with PLLs (e.g., PICs with superlative core clock) are one example.  I want to say I've come across such a warning in an ATmega datasheet as well.

FWIW, I've played with a Z80-CPU before; this is 1980s vintage NMOS (all built from N channel FETs and pullup resistors only -- the sucker takes 200mA at 5V regardless of clock rate or bus activity!), which contains dynamic logic and, I believe, pooped out much below 2MHz or above 6MHz (rated for 4MHz nominal).  Crappy clock signals cause the core to simply freeze.  The earliest problem I had with it was power-up: a crystal oscillator requires miliseconds to stabilize, in which time the CPU has already forgotten what it was doing.  A power-on delayed reset circuit is mandatory for this type of circuit -- and recommended for pretty much everything else, too (apparently, ATmegas have problems with very slowly rising power supplies -- better safe than sorry, use a reset circuit).

Tim

[David Hess]

Static logic should also not depend on the rate of change either, so beware: even apparently static designs may have dynamic elements in them.  Point being, I believe I have read a few datasheets which state that the clock frequency shouldn't be removed or changed suddenly, but gradual over some rate.

Static CMOS logic may include transfer gates as a logic element and they are not slow transition time friendly.  The same logic though often includes schmitt trigger inputs for the clock making this irrelevant.  Various edge triggered flip-flops fall into this category.

Dynamic logic of one form or another used to be common but in all but the highest performance applications, it has been replaced with static CMOS logic.