Clock pulse offset circuit?

[bitman]

I'm reposting - or maybe trying to remember to hit POST this time. IF for some reason my previous post on this was removed please let me know why.

In my TTL CPU project I need to create a derived pulse about 80ns shifted from the pulse I already have. I have a few chips like memory that can take that long to get output ready, so I need to split the clock between the "slower" chips. Unfortunately my google foo is not up to snuff here - I get a lot of patents on much more complex circuits creating 6, 8 or more separate frequency intervals. I like the idea of using flip-flops but I cannot find something that tells me how to calculate the time a flipflop takes.  I've also thought about the non-overlapping 2-phase frequency that seems a bit extreme though when all I want is a slight pause between the signals, and I would still like the "write" to be high/active while reading is going on.

I'm on a learning quest so I'm really looking for something to explain how things work, so I can understand why circuits would be designed this way, and figure out how to adjust it.  I did btw. try a few inverters and that only gave me about 20ns or so.  I don't have a ripple counter IC available, and I did find some materials that advised AGAINST using ripple-counters for this.

So I'm looking for sources can help me understand how to do this. Thanks.

[rfeecs]

Try searching for delay line.

[David Hess]

80 nanoseconds is pretty long for a gate delay or delay line but just about right for an RC network buffered by another gate; include a diode for a fast reset.  I suppose a couple low power TTL gates could be used in series but I think the RC delay is a better option.

[bitman]

80 nanoseconds is pretty long for a gate delay or delay line but just about right for an RC network buffered by another gate; include a diode for a fast reset.  I suppose a couple low power TTL gates could be used in series but I think the RC delay is a better option.

The chip I have is http://www.jameco.com/Jameco/Products/ProdDS/391822.pdf (CY62256LL-70PC). If I read the data-sheet correct, it has a 55-70ns response time? It's definitely a lot slower than the other TTL chips I have.  About the RC delay, maybe I designed it wrong but I didn't see a delay - and even worse, the pulse was not good enough to drive more than one or two chips at a time. I probably should look more at this again. 

Is this the type of circuit you're talking about? http://www.ecircuitcenter.com/Circuits/opfil1/opfil1.htm

[David Hess]

That is the circuit but the amplifier is replaced with a logic gate.  For TTL, I think it needs like 3 RC time constants so like 1k ohms and 220 picofarads.  The values can be trimmed to get the exact delay that you want.

[rfeecs]

There's a temptation to say that if you need a delay you are doing it wrong.  The usual way to deal with slow memory is with wait states.  Assert the address lines, then wait some number of clock cycles before reading or writing.

For the RC delay, it would probably be a series R, shunt C, followed by s Schmitt trigger.  You need the Schmitt trigger to give you a good rise/fall time.

[bitman]

An additional question - does the wave form (sinus vs. square) make any difference?

[bitman]

There's a temptation to say that if you need a delay you are doing it wrong.  The usual way to deal with slow memory is with wait states.  Assert the address lines, then wait some number of clock cycles before reading or writing.

I was wondering about that, however it seems logical (excuse the pun) to time reads and writes differently?  Why have chips accept input when the state isn't ready?  Granted, what I am about to do will really limit the maximum speed of the clock and if this was anything but a demo system I would follow your advice. But my basic question is still, that having differently timed clocks for read and write make sense - take away the extreme time difference in my case?

For the RC delay, it would probably be a series R, shunt C, followed by s Schmitt trigger.  You need the Schmitt trigger to give you a good rise/fall time.

Thanks I didn't have the Schmitt trigger on it before. I'll get on that.

[bitman]

For the RC delay, it would probably be a series R, shunt C, followed by s Schmitt trigger.  You need the Schmitt trigger to give you a good rise/fall time.

Thanks - this worked. Turned out my inverter was "just" that, not the schmitt version, which I had no clue I had a few off - so I simply had to replace my 7404 with 7414 and connect me RC and I very close. I changed the cap, and now the delay is long enough. Thanks.
How do you calculate the sizes of the resister/cap in this setup? Ie if I know the length and mA/Volt how can I determine the delay?

[bitman]

That is the circuit but the amplifier is replaced with a logic gate.  For TTL, I think it needs like 3 RC time constants so like 1k ohms and 220 picofarads.  The values can be trimmed to get the exact delay that you want.

So that's what I had, but I guess I m issed the Schmitt Trigger requirement because once I replaced my TTL it worked.  I'll ask you the same question though - what formula do you use to determine the values of R/C in this setup?

[David Hess]

That is the circuit but the amplifier is replaced with a logic gate.  For TTL, I think it needs like 3 RC time constants so like 1k ohms and 220 picofarads.  The values can be trimmed to get the exact delay that you want.

So that's what I had, but I guess I m issed the Schmitt Trigger requirement because once I replaced my TTL it worked.  I'll ask you the same question though - what formula do you use to determine the values of R/C in this setup?

Ultimately it is just the exponential curve from charging a capacitor through a resistor:

https://en.wikipedia.org/wiki/RC_time_constant

In practice a given type of logic will yield delay = K * RC where K depends on the input and output characteristics of the logic family. 1 * RC is one time constant of delay so designers often talk about 1.2 or 2.2 or whatever time constants.