Common Ground or Offset issue?

[ChrisG]

Hello all,

This is my first post here and apologies if I was not able to find similar topics on your forum already. I did try to find here and on Google answers to my problem/question. I'm having a Z80 CPU kit from http://cpuville.com/Z80_kit.html which was really fun to build. Now wanting to play with it and run it at lower frequencies then the preset 2Mhz I wanted to connect my SDG2042X to the clock path (while disabling the onboard clock of course). Did not work at all and was fiddling for a whole weekend some time again. Eventually fried the Z80 even. Measuring and re-measuring between onboard and Siglent levels I noticed on the scope that the Siglent one, while ground was common, had a lower ground signal then 0v. Not by much but for what ever reason, which I do not understand, I had to UP the offset to 2v on the Siglent and I can control the speed of the Z80 pretty well down to about 10Khz. The lowest frequencies still do not work.

SDG is connect with 50cm normal wire out of a BNC connection. HiZ impedance is on. 2V offset and 4Vpp. 50% square wave.

I'm looking for advice and learnings on what is happening here.

Many thanks if people can chip in

[newbrain]

Welcome to the forum, ChrisG!

Starting from the second question:
According to this datasheet, page 80 or 82, the maximum clock pulse width, low, is 2000ns, at 50% duty cycle that would make 250kHz (ignoring rise and fall times), so you are already lucky to have got it down to 10kHz.
You might try changing the duty cycle while lowering the frequency.
If you have a CMOS version of the Z80, though, there should be no such limitation.

[...]while ground was common, had a lower ground signal then 0v

If the ground was common, you are probably referring to the lower part of the output square wave.
In general, the output of a signal generator is centered around 0V, and that's the reason you had to add a 2V offset: to bring a +2/-2V output (4Vpp, ground centered) to 0/+4V.

If the connection was direct and the signal generator has low output impedance, it's possible you fried the Z80 by exceeding the maximum current on the input clamp diodes, reading the SG manual it seems that the HiZ setting is only useful to give correct output voltage reading, and is not changing the actual output impedance.
The Z80 datasheet at page 79 states an absolute minimum of -0.3V at any pin, while you were applying -2V.

So, a raw estimation of the current (assuming 50ohm SG output impedance): (2-0.3)V/50ohm = 34mA, quite enough to damage the chip.

[danadak]

Key issue with CMOS is you cannot drive a pin (there are some exceptions) outside the supply
rails. It will trigger a parasitic SCR in the CMOS structure which will short internally the supply rails
and blow out the VDD/Vss bond wires to the parts leadframe.

When I work on processors with instrumentation I almost always use a 1K r between the instrumnent
and CMOS pin when setting up, to make sure I don't forget to set up the generator, or whatever. Then
remove the 1K when I am sure I am good to go.

https://www.fairchildsemi.com/application-notes/AN/AN-339.pdf

http://vlsiuniverse.blogspot.com/2013/03/latchup-condition-in-cmos-devices.html



http://www.microsemi.com/document-portal/doc_view/126494-msan107-appnote


Regards, Dana.

[newbrain]

Key issue with CMOS is you cannot drive a pin (there are some exceptions) outside the supply
rails. It will trigger a parasitic SCR in the CMOS structure which will short internally the supply rails
and blow out the VDD/Vss bond wires to the parts leadframe.

I did not think about latch-up when answering, but...
Honest question: does this happen also with NMOS chips (as the original Z80)?
I would say not: given the absence of the negatively doped regions for the PMOS channels, there should be no "base region" for the parasitic PNP in the SCR.

[ChrisG]

Gentlemen,

Thank you so much for sharing all that information. After your posts and comments I rechecked some items and indeed I can go lower in the frequency as long as I adjust the duty cycle to 85% or so. The Z80 is a Z8400 PS from the year '84. So NMOS it is. I then "forced" myself to read the Art of Electronics chapter 10 and this too brought me back on track on TTL voltages and the difference with CMOS.

[danadak]

No latchup in NMOS as there is no PMOS parasitic to form the feedback
loop to create latching.


Regards, Dana,