Control Duty cycle with (logic gates,Flip flop etc)

[christos]

Hello!
Is there any way I can control the DC% with flip flops or gates. at 100hz?
I want to control a servo motor using Logic gates and flip flops.

Thank you!

[Ian.M]

Not easily with pure logic gates and flipflops, however if you allow the use of monostables available in most logic IC families, its pretty easy.  e.g. see fig 13 of http://www.ti.com/lit/an/sdla006a/sdla006a.pdf

[retrolefty]

Hello!
Is there any way I can control the DC% with flip flops or gates. at 100hz?
I want to control a servo motor using Logic gates and flip flops.

Thank you!

 Well I have seen a zillion 555 timer chip circuits used to operate hobby type servos that require a 1 to 2 millisec variable pulse width at a 20-25 msec frame rate. Many RC servo testers on Ebay.

[Benta]

christos, not in an easy way. You'll need to define what kind of resolution your PWM needs. An analog PWM theoretically has infinite resolution, with a digital you risk servo jitter.

A solution using programmable counters is possible, but will be large.

[christos]

Thank you for the replies!

I'm currently trying to make a block diagram in Quartus to program the FPGA . I need to make at least 1 servo move

The frequency that the servo will work is at 50Hz (20ms) with duty cycle from 1ms to 2 ms (servo model SG90)
I made a frequency divider from 50MHz to 50Hz but I stuck there, I tried to use a comparator but no luck there too.
Thats why I'm trying to figure another way to make it work


and I cant use a 555 timer or the 74L123!

Thank you again!

[Benta]

There are several ways to do this.

One idea is to use two programmable (down) counters in parallel. Both are loaded at the same time, one runs at your desired 20 ms period, the other at your variable pulse length. Gate the outputs together, and you have a solution.

Another idea is to run just one 20 ms counter, and decode its output.

And, and, and...

[tautech]

The VCO in a 4047 or some configuration using 4046 or both.

[mvs]

I'm currently trying to make a block diagram in Quartus to program the FPGA . I need to make at least 1 servo move

The frequency that the servo will work is at 50Hz (20ms) with duty cycle from 1ms to 2 ms (servo model SG90)
I made a frequency divider from 50MHz to 50Hz but I stuck there, I tried to use a comparator but no luck there too.
Thats why I'm trying to figure another way to make it work

Sticking together glue logic on block diagram is not a proper way to design for a FPGA.
Hier is a code example for two channel PWM modulator for RC servos written in verilog. In Quartus you can generate a component symbol out of verilog file and use it on block diagram.
You need to supply 10KHz clock to clk input and some input values to PWM_A and PWM_B. Resolution is 0.1ms or 1/10. You may add more channels if you like.

Code: [Select]

module PWM(
    input clk,
    input [3:0] PWM_A, PWM_B,
    output OUT_A, OUT_B
);

reg [7:0] cnt;    // free-running counter register
reg [4:0] comp_a;    // compare reg channel A
reg [4:0] comp_b;    // compare reg channel B

always @(posedge clk)
begin
  if (cnt==8'd199)
    begin
      cnt <= 8'b0;    // reseting counter on cnt==199
      comp_a<=PWM_A + 5'd10;    // loading comp_a with PWM_A + 10 on counter reset
      comp_b<=PWM_B + 5'd10;    // loading comp_b with PWM_B + 10 on counter reset
    end
   else
      cnt <= cnt + 1'b1;    // incrementing counter
end

assign OUT_A = (comp_a > cnt);    // comparing comp_a with cnt and assigning result to OUT_A
assign OUT_B = (comp_b > cnt);    // comparing comp_b with cnt and assigning result to OUT_B
endmodule


[christos]

I think this will work fine. Thank you!
But what kind of values do I need to set on PWM_A and B.
I get 3 inputs for PWM_A and 3 inputs for PWM_B

I'm kinda new to FPGA.

[mvs]

Inputs have 4 bit width. 0000 corresponds to 1ms, 0001 - 1.1ms, 0010 - 1.2ms and so on.