Author Topic: Current limiting of a SMPS  (Read 6459 times)

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Offline ANTALIFETopic starter

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Current limiting of a SMPS
« on: November 10, 2015, 04:59:27 am »
Hello


What sort of techniques would you use to limit the output current of a switched mode power supply?

For example let's say I have 12V @ 1A going into a buck converter and have my output set at 5V (having a magical 100% efficient converter means max output current would be 2.4A), but I want to be able to limit the output current to a value between 0.1A and 2A. Knowing this what sort of component would I use to achieve this? So far I can only think of using a BJT and varying the base current to control collector current.


Cheers, Ivan
« Last Edit: November 10, 2015, 05:30:27 am by ANTALIFE »
 

Offline nowlan

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Re: Current limiting of a SMPS
« Reply #1 on: November 10, 2015, 07:35:21 am »
I would have fed it into a Low drop out (LDO) regulator. The datasheet will show how to current limiting works.
http://www.st.com/web/en/resource/technical/document/application_note/CD00003773.pdf

Otherwise the buck convert will have somethign similar. You may be able to replace a fix resistor with a POT to control current.
 

Online T3sl4co1l

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Re: Current limiting of a SMPS
« Reply #2 on: November 10, 2015, 01:16:39 pm »
By design, or by addition?
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Offline ANTALIFETopic starter

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Re: Current limiting of a SMPS
« Reply #3 on: November 10, 2015, 09:49:26 pm »
What sort of things would the two involve?

Offline ANTALIFETopic starter

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Re: Current limiting of a SMPS
« Reply #4 on: November 10, 2015, 10:35:27 pm »
The blue part is what you expect to be in a cc buck converter, the red part is what you can add to make is cc-cv.

This is called a cascaded loop, where the inner loop is voltage loop, and the outer loop is current loop.

Capacitors in voltage feedback network and current feedback network needs to be carefully calculated and simulated to ensure stability.

The buck converter should better be a synchronous one operating in forced CCM mode, to try to make sure transfer function is predictable (not guaranteed with any load resistance).

Wrong post?

Online T3sl4co1l

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Re: Current limiting of a SMPS
« Reply #5 on: November 10, 2015, 11:16:31 pm »
What sort of things would the two involve?

By design is best.

A proper SMPS has an inner control loop which regulates inductor or switching current.  Limit that variable, and you limit output current, period.

Normally, a voltage error amp controls that variable, to get regulated output voltage.  But if you put a limiting circuit after the Verr amp, you can prevent it from calling for more current.  Hence, you get a "square" operating curve (CC on one side, CV on the other).

This way, the circuit is always 100% in proper regulation, either cycle to cycle (e.g., peak current control), or over the duration of only a few cycles (average current control), simply as a matter of fundamental operation.  Whether it's in current or voltage regulation is up to the control stuff out front, which is unable to screw things up by forcing the switch to stay on, or something (unlike voltage-mode and direct PWM controllers, which are unsafe for this reason).

As for integrated controllers, like blueskull's example above, try to get the kind with a compensation pin.  This is usually the gain node of the internal voltage error amp.  Normally, this pin has an R+C to ground, or to the FB pin.  In either case, you can clamp the pin voltage to get a programmable current limit, or drive it directly for CC mode.  You'll have to check the internal diagram to be sure this is actually possible, of course.

The kind with fully internal compensation, as in the diagram, are just about impossible to work with.  Notice that the left red op-amp has no compensation, just a diode to the feedback pin.  Note also that the feedback pin necessarily has extremely high gain, so once the diode is forward biased, the op-amp output should be expected to move very little.  But the op-amp is, well, an op-amp, and itself has extremely high gain.  As shown, it's a relaxation oscillator, and will oscillate at a modest fraction of the switching frequency (maybe 1/10th and below).  It can be stabilized by slowing things down, but this is uselessly slow: loop bandwidth must be below the dominant pole of the internal error amp, probably under 1kHz!

Here's an example of a complete system with:
- Peak current mode control
- Current regulation (primary purpose)
- Voltage regulation (secondary, soft limit)
- Temperature regulation (secondary, soft limit)
- Isolated error amplifier
http://seventransistorlabs.com/Images/LED_Light.png

The voltage and temperature limits are implemented as constant currents, which offset the error amp's feedback input.  Very much in the same spirit as the above example.  They have intentionally low gain, which prevents them from oscillating, but makes the limits very "soft".  Since voltage limiting is only needed for protection, and temperature is imprecise and slow, this is acceptable.

If you need precise regulation, not soft limits, this is not a practical approach.  Instead, you'd limit the voltage on UC3842 pin 1, which is its peak current setting pin (which comes from the internal error amp, which itself is simply being used as a gain-of-1-inverter, because there's an error amp elsewhere in the circuit).  Peak current isn't exactly the same as DC output current, but it would be pretty close, and can be improved with another error amp.

Tim
« Last Edit: November 10, 2015, 11:25:34 pm by T3sl4co1l »
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Offline ANTALIFETopic starter

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Re: Current limiting of a SMPS
« Reply #6 on: November 11, 2015, 01:38:57 am »
Wowsers, thanks very much for that fellas off to do more research then.


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