Data and synchronization signals on the same wire?

[m4rtin]

I read Network Maintenance and Troubleshooting Guide book and in paragraph where Ethernet frame preamble is explained, it says that except for 100BASE-T4, faster versions of Ethernet are synchronous. Is it possible to keep both data and synchronization signal on the same signal path?

[retrolefty]

Is it possible to keep both data and synchronization signal on the same signal path?

 Of course, that is how synchronization links work, a clock is 'extracted' from the data stream with additional hardware both on the transmit end to 'ensert' the clock information and at receiver end to 'extract' the timing information. Note that many/most micros these days have USART hardware build in, so most of this all ready avalible. Check out a typical AVR datasheet for a description of the USART options.

[m4rtin]

Is it possible to keep both data and synchronization signal on the same signal path?

 Of course, that is how synchronization links work, a clock is 'extracted' from the data stream with additional hardware both on the transmit end to 'ensert' the clock information and at receiver end to 'extract' the timing information. Note that many/most micros these days have USART hardware build in, so most of this all ready avalible. Check out a typical AVR datasheet for a description of the USART options.

I see, thanks! How is the clock signal differentiated from data signal? Is it with different voltage?

[helius]

I think that is kind of a half-truth, all types of Ethernet are synchronous in the sense of not having start and stop bits. The only important difference between 100BASE-T4 and the rest is that it uses all four pairs of cat3 at a lower modulation rate than 100BASE-TX (which requires cat5 because of its higher bandwidth). The data signal is differentially driven over twisted pair, and is self-clocking. On lower speed links that is achieved with Manchester coding, which is a self-clocking code with a coding efficiency of 1:2, whereas on higher speed links like 1000BASE-T it is a code like 8b10 or 64b66 with much higher efficiency.
The clock is extracted by having the sender and receiver both use an accurate reference frequency, sending a framing burst before each data packet, and a special PLL in the receiver that locks onto the frequency of the framing burst. Similar techniques are used everywhere, from CD-ROMs to wifi.