How are you getting your 3.3v supply? A 1.5vpp signal applied though a 100k resistor shouldn't cause a large fluctuation on it. (and there should be capacitance on the supply already for the op-amps )
The circuit you attached should work just fine if you have bypass caps on the opamps. If not definitely add those. You will have a cutoff of 3.2Hz, If you want response to DC, you'll need an op-amp to add a DC offset, but if you're fine with down to 3.2Hz, then just using the op-amp as a buffer is fine.
I'd keep the op-amps too, as many ADC's have a low(ish) input impedance and that would vary the roll-off caused by C67. For example, if the ADC had a 5k input impedance, that would push the cut-off upto 30Hz.
If you really want to keep your noise separated out. I'd use a regulator for the analog side and the analog side of the ADC power, and a second regulator for all the digital stuff. and I'd use star grounding if you dont have a big ground plane(I.e. breadbording or protoboarding).
EDIT: the 3rd schematic you posted would have a static DC offset as desired and frequency response down to DC. However your divider for 1.6v should probably be 1k and 1k or lower so that the 10k resistor doesnt load it too badly. As it is now, it would be loaded down to 1.1v, because U6 pin 2 is going to be held at agnd potential by the op-amp.