DDR3 routing

[subzero]

Has anyone routed a DDR3 BGA to an Allwinner A13?  I'm just learning how to do the routing between these two chips, and just wanted to ask a few questions.  I have set up a mock test scenario (the signal paths between DDR3 BGA and the A13 processor), and came across something kind of annoying while routing the first data lane (DQ[0:7], DM0, DQS0+/DQS0-).  The DM0 and DQS0+/DQS0- signals overlap while routing, which is a bit of a shame, because all of the data bits route nicely.  What would designers usually do in this case?  Route the DM0 signal on another layer, and leave the other signals on the top layer, or (as recommended in a lot of datasheets), route all the signals exactly the same?  This seems to be the only problem, as the other data lane doesn't overlap at all, which would make it a bit of a shame if I had to route the lanes on different layers.  I guess I could wrap the DM0 signal around the DQS0-/DQS0+ signals, but that seems... umm... I guess that could be done come to think of it.

Ideas / recommendations?  Tips for placing the decoupling capacitors?  Tips for length tuning these signals?  How would designers generally tune the data lanes?  Waves, or by introducing longer lengths by hand?

Thanks!

[PhillyGreg]

Do you have a screenshot showing both the processor and the RAM?

A couple questions and a few thoughts that come to mind.
How many layers are you targeting, and what are your design rules?
What CAD and simulation tools do you have?
What speed are you looking to run the memory at?

Micron TN-41-13 is a pretty good reference if you haven't looked at it yet. (It has suggestions on placement for decoupling capacitors)
Do you have any known working layouts for the A13 to reference?
It can be best not to reinvent the wheel if you don't have to.

Also looks like you are using a x16 chip. I'm wondering if the processor was setup for a clean layout with two x8 chips.

[RoadRunner]

yes i have done , here is the look at image from ddr3 route


i have look closely where you are stuck.

complete project lies here
www.circuitvalley.com/2015/11/linux-board-homemade-pcb-design-ddr3-schematic-altium.html