Decoupling capacitors are mysterious.

[fatlimey]

Hello, love your show!

I'm an enthusiastic beginner, blown up my fair share of parts poking around, but I do love putting together kits that other people have designed. Learning how they work and, more importantly, how they came to design it that way in the first place.

While assembling kits I have diligently added decoupling capacitors wherever the design says so, but I have absolutely no idea how one goes about working out where to put them and what size to use. How do the designers know "Ah, a 200pf right... here will do the trick"? Are they just guessing? Poking around until the weirdness disappears? That might work on a small device, but then how do these things get done on large PCBs like CPU motherboards?

It seems like a black art to me, especially on digital circuitry. I fully understand digital logic but what kind of mindset helps you look at digital devices also as analog devices?

Thanks for any insight you have,

- Fatlimey,.

[Mastro Gippo]

I usually add them following datasheet specifications. They usually tell you where to put caps and their values. I then add a bunch of caps on the supply, within the limit of the regulator, just to be sure. Usually, when you know your signals, you will know if you have spikes to damp and choose your own cap based on the input impedance and such. 

[ianbanks]

Once you get into higher frequencies (above DC) any inductance or capacitance acts like a resistance. The inductance of the long path back to your supply causes voltage drops when there are switching transients in the digital IC, just as the resistance of a long wire would cause a voltage drop when supplying some distant load.

Decoupling capacitors "bypass" the longer more inductive lines back to your supply; rather than the current running in a loop right back up to your power supply, they allow it to run in a much smaller loop out of your chip and through the capacitor.

The impedance of a capacitor is frequency dependant, and decreases with frequency (the "resistance" of a capacitor near DC is very high--like an open circuit). So you need a high value that has a sufficiently low impedance to cover the lower frequencies. These tend to be "bulk" values (uF range). The problem then is that at a certain point, the parasitic inductance of a large value capacitor starts to _increase_ the impedance at higher frequencies. The solution is to parallel another capacitor of a lower value. That's why as clock speeds get higher you see more de-coupling capacitors at differing values.

The other thing that helps most high speed boards is the capacitance of the supply and ground planes in the PCB.

If you want to learn about the actual values you'd need to use, or more about the subject in general, you need one of:

http://www.amazon.com/Signal-Power-Integrity-Simplified-2nd/dp/0132349795
http://www.amazon.com/exec/obidos/tg/detail/-/013141884X
http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241

The first two would be good for a beginner (even a non-engineer). The third one is a classic, but there is a new edition coming out soon.

There are some notes online from the second book online:

http://www.ultracad.com/article_outline.htm

In particular:

http://www.ultracad.com/mentor/esr%20and%20bypass%20caps.pdf

But you may want to read the introduction sections of one of the first two books before tackling the details.

[fatlimey]

Thank you.

Looks like I've got me some new bedtime reading!

- Fatlimey.

[EEVblog]

Ian has covered it well.
But the basic answer is that, in general, when it comes to decoupling capacitors we just pretty much pick the value out of the air.
Why? Well it's extremely difficult, if not impossible to accurately calculate sometimes, and it's not actually going to matter too much as whole range of value will do the same job. There are so many interacting variables like lead inductance, trace resistance/inductance, plane capacitance/resistance/inductance, and the list goes on. Some people try and model it, but most just throw in a value they know will roughly work based on experience.
So when you see a 100nF decoupling cap, there is no major reason for that value, apart from it being in a rough ballpack and a nice round figure. How about an oddball value like 2.2nF ? Well, maybe it's just because they have used that value elsewhere on the board, so it was convenient and they needed something smaller than a standard 100nF. You get the idea!
Often you just need "something" there, and the actual value doesn't really matter to a point.

Yes, we also "poke around until the weirdness/problem disappears"!
Say your prototype works but doesn't pass some EMI test (radiating too much noise). You might throw a few caps around and see how it changes, usually you'll nail it on the first few goes. Trying to calculate and model the whole system could take years and an entire PhD thesis! So you just throw a cap here or there (once again based on experience of the likely culprit) until you fix it. Then you measure the performance you are interested in to make sure it's all hunky-dory.

And yes, follow the manufacturers datasheet or app note recommendations is the usual way to go. Where do they get their value from?, see above! A lot of electronics is "warm and fuzzy", not the clinical calculated ideal stuff you learn in school.

It's not all like that of course, there are times when you need to accurately calculate values like this for some apps.

Dave.

[Simon]

for large powerful supplies caps are put in paralel so that the overall capacitance reacts faster (charging and discharging), for large cicuits its a general rule to use a 100 uF and a 100 nF in paralel as physically close as possible to the supply pins of each IC, a good experiment is to set up a pic using the PWM output and have a set output, power the pic's board/breadboard from a long wire say 2 metres, now use different decoupling caps and whatch the change in the quality of the output waveform on a scope, this may work with a 555 in astable mode but don't quote me on it

[bmwm3edward]

Very cool to see the "real world" approach vs. theory.  I've worked in software for 15 years and the same BS is used to get crap out the door.  There's theory, and then there's real-world "Get-R-Done" principles.  For me, I'm happy to know where those real-world solutions trump the endless theory that would otherwise leave me stuck in some book for weeks before I would feel competant enough to get on with the design -- thanks Dave!

[Simon]

I'm afraid that there is lots of theory that cannot be applied and taken on face value, there will always be physical/practical implications because we live in a real world

[Neilm]

The size of the decoupling capacitor is dependent on the speed the chip ACTUALLY operates. If you have an IC that is only operating at 1Mhz but is capable of operating at 100MHz you will find that the outputs will change state at the speed required for 100MHz operation. This will require capacitors that can react to this. Generally what you will find is that you will have a large capacitor for general decoupling (100uF) and a one or more smaller caps for higher speed requirements. (100nF, 1nF) If you ever look at a circuit that operates at GHz frequencies, don't be surprised if you see decoupling caps of 10pF or less.

[Dago]

Selecting decoupling capacitor values is one thing where practical experience really matters. In practice you usually just pick a value that sounds right for the frequency/application. In a nutshell the higher the frequency is the touchier it gets. One thing to watch out for is the caps resonating.

[ianbanks]

I think the "Go Real World", "Die Theory" posts have misinterpreted Dave's comment.

Dave pointed out that you usually guess (based on experience or by similar designs) or go with the manufacturers recommendations (which are usually available for devices with more difficult requirements) rather than calculating the value, which is true.

Any book on the topic will point out (around the same place they show the calculations) that it is impossible to completely model and calculate the required values because the exact requirements of the chip are generally unknown to anyone but the manufacturer and because an accurate model of your own power supply is also difficult to determine.

That doesn't mean you can get away with not knowing what is actually going on. If you've never seen the theory you may not even know which way to tweak things (bigger capacitors are always better, right..? ..!) or how to solve a problem you've run in to.

Also, I'm a technically a software engineer, and I hate working with programmers that don't own books (which would be most of them). There is plenty of room between a PhD and a cookbook/cookie cutter programmer, and the best programmers are somewhere in between.

[Ronnie]

If you want to learn about the actual values you'd need to use, or more about the subject in general

This is also a good reference from Analog Devices read section 7-3 pages 66 to 74 http://www.analog.com/library/analogDialogue/archives/39-05/Web_Ch7_final_J.pdf

[Vertigo]

quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?

[sacherjj]

quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?

Dave did a good video a while back about the various capacitor types.  That would answer some of your questions.   But these are just normal caps in a specialized use case.

Let's see...  Episodes 33 part 1 and 33 part 2.

[Alex]

quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?

Some authors in EMC literature treat them as the same. The distinction is made on the basis of capacitance value and position in the circuit, but the theoretical treatment is the same.

Alex

[Vertigo]

ic thxz

[Zero999]

I wonder why no ICs ever come with decoupling capacitors built in?

This would probably only be any good for high speed parts of course. Surely etching a 100pF capacitor onto the die near the power supply pins would help a lot, even if it still required a larger external capacitor. Another idea would be to encapsulate a small ceramic capacitor in the casing so it's nearer to the die. Built-in capacitors would also help to simplify PCB design as well as increase the operating speed.

[gregariz]

I wonder why no ICs ever come with decoupling capacitors built in?

Everything is possible but as a general rule capacitors take up alot of die space since they tend to be physically large for any decent capacitance.

Years ago, they used to sell IC sockets for the standard DIP packages that had a 0.1uF cap across the standard pins, so you didnt need to remember to put down 0.1uF everytime you placed a logic chip.

http://www.conrad.com/IC-sockets-with-capacitor.htm?websale7=conrad-int&ci=SHOP_AREA_27787_0205025

[gregariz]

It's not all like that of course, there are times when you need to accurately calculate values like this for some apps.

For higher frequency circuits and sometimes an audio circuit, I typically use a RC circuit to decouple, the circuit will look the same but with a series resistor added between stages and you'll be looking for a time constant based on the frequency you are trying to decouple. Generally you try to make the resistor as small as possible so you don't lose your voltage so some of the caps can be pretty large, it depends on the frequency really. But in this case I would advise you to calculate it. Otherwise as others have said you are simply moving around your circuit looking to short any AC on the DC rails to ground and any old low inpedance cap will do. At microwaves I'll use a sequence of caps of differing values in parallel since I am looking to shunt a wide range of frequencies to ground. The caps at a high enough frequency stop being caps, they have self resonances and many have nasty series resistances, so a spread of values helps you out here.

[jahonen]

Apropos, I did a measurements using a spectrum analyzer (R&S FSV7) with a tracking generator a while ago about which bypass capacitor arrangement is best combination and arrived to a conclusion that it seems to be best to simply just put many as large-valued as possible capacitors in physically smallest package (smaller package = less inductance, thus higher resonant frequency) in parallel. This result agrees with one book I have about EMC, where the author arrived at same conclusion. For comparison, I also measured wide copper tape (any capacitor is likely not to be better than this, but clearly copper tape causes difficulties at DC) soldered/glued in place of the capacitor(s). It seems that the jig geometry is the limiting factor here. Narrow copper tape is copper tape just wide enough to bridge the cap. Setup is sensitive enough to distinguish if copper tape is soldered or just connected using a conducting glue.

If anyone has different results for real-world measurements using a realistic geometry, and not just theoretical idealized speculation, I'd like to see them. Different values gave parallel resonances which hampered the result, whereas paralleling same value reduced the impedance for whole spectrum (6 dB improvement on impedance when doubling amount of capacitors).

Thus, how the capacitors are connected (geometry), is at least as important than the capacitors themselves. As you can see, 4 paralleled 100n capacitors are better than equivalent amount of different valued capacitors, except for narrow frequency bands.



Making a seemingly simple short circuit at high frequencies is very difficult. Even slightest inductance spoils the whole show. Here is the jig, set up with copper tape. Of course, when capacitors are measured, the copper tape is removed.



Regards,
Janne

[ejeffrey]

One way to look at it is this: you want the voltage supply *to the chip* to be the same no matter what.  An interesting characteristic of CMOS logic is that it draws almost no power in steady state, but very fast chips like 74AC logic can draw an amp for a nanosecond while switching states.  The large peak current means you need a low resistance to avoid a large voltage drop, and the fast rate-of-change of current means you need a low inductance.  You need a charge storage device that can respond to very fast changes in load.

In very critical circuits you may need to have multiple decoupling capacitors -- for instance a 100 nF capacitor using a high-K dielectric can store a lot of charge, but is a bit slow to respond.  You may need a 1-2 nF device in parallel with a low-k dielectric that has an extremely low series inductance and resistance. 

Finally, you may have to worry about resonances between the bypass capacitors and the effective inductance of the PCB trace or the voltage regulator.  If this happens, there can be a certain characteristic frequency at which there is a parallel LC resonance and corresponding high impedance.  If the load current varies at near that frequency, there will be a large voltage drop on the LC circuit and the IC will see a large time-varying voltage.  The usual way to handle this is to add a small (like an ohm) resistance into the supply line.  Ideally this damps the high frequency resonance while not degrading the low frequency behavior unacceptable.

[mikeselectricstuff]

Just for idle amusement, I did an experiment a while ago - on a 2-layer board with FPGA running at 36MHz driving quite a lot of I/O, I took off all the decupling caps, leaving just a single 1u ceramic on the 1.8 and 3.3v regs and it still worked fine...
Not suggesting it for production though..
Nowadays my default decoupling caps are 0805 1u X7R ceramics, as costs is the same as 100n and eliminates the need for larger bulk decoupling. I only use 100n when space is tight.   

[Neilm]

Just for idle amusement, I did an experiment a while ago - on a 2-layer board with FPGA running at 36MHz driving quite a lot of I/O, I took off all the decupling caps, leaving just a single 1u ceramic on the 1.8 and 3.3v regs and it still worked fine...
Not suggesting it for production though..
Nowadays my default decoupling caps are 0805 1u X7R ceramics, as costs is the same as 100n and eliminates the need for larger bulk decoupling. I only use 100n when space is tight.   

Something like that might still function correctly, but you probably had a lot of EMC emissions.

Neil

[Relaxe]

Hello all, sorry for bumping a very old (but always actual) topic.

First, thanks to jahonen. That is one of the most straightforward test I have ever seen on the "decade myth".
In book "PCB Design for Real-world EMI Control", by R. Archambault. ISBN 1-4020-7130-2 http://www.amazon.com/dp/1402071302
At chapter 8.4, there is 16 pages explaining a very similar experiment, but on a much larger scale: 15 SMA connectors and 60 capacitor locations.
The conclusions are the same: Take the largest value you can both afford and have space for, knowing that for the same value the smaller packages performs better.

Also, a tool from TDK shows the frequency response of their ceramic capacitors. Here is what I have plotted. Notice how package size impact the inductive right part, and the value iMpacts the capacitive left part. Also notice how little the "100pF" /they/ tell us to add with the 0.1uF does next to nothing below 750MHz.


Hope you enjoy this!

[CarlG]

I wonder why no ICs ever come with decoupling capacitors built in?

Some FPGAs and processors come with decaps builts-in. Check e.g. Xilinx Virtex series.