It seems like a black art to me, especially on digital circuitry. I fully understand digital logic but what kind of mindset helps you look at digital devices also as analog devices?
Thanks for any insight you have,
- Fatlimey,.
There are (at least) two ways to look at a capacitor for decoupling: as storage for charge, and as a "impedance shunt". The first is for supplying charge to the capacitive load, the latter to shunt the inductive reactance on the collector/drain of the output transistor. [I refer to 'output' even though the driven node may be internal.]
First, simultaneous switching outputs is one parameter to consider. If you have a device driving a (large) capacitive load (say 32 bit address and 32 bit data with 50 pF on each output) you have 3.2 nF total load. In order to avoid a voltage drop of say 5% at the closest located (ideal) "decoupling" capacitor, you'll need 19x the load, i.e 64 nF. (capacitive voltage divider) However, the rise time of modern logic is so short so in practice you'll need plane capacitance to avoid local voltage drops due to the inductance between the decap and device. This also helps prevent EMI. For small devices and/or small Cloads, the plane capacitance naturally gets less important.
Note that this implies that the decap only is "active" for low-to-high transitions. For high-to-low transitions, a low inductance return path is needed to avoid ground bounce. The decap is not involved.
Secondly, the output stage might be seen as a open emitter/source stage. The gain is g
mX
C, and g
mX
D, respectively. The decap obviously keeps the gain down, which is what you want to avoid oscillations. This is just like any analog amplifier stage.
The reactance of the decap vias quickly dominates over the plane inductance, meaning that the location is not critical if you just consider a simple case (one driver, one load),
assuming that the decap is directly coupled to power/gnd planes. However, the decaps must be placed so that transients currents doesn't disturbed other, more sensitive parts.
Altera has a spreadsheet for help on calculating the proper decoupling, usable for general purpose; not only for Altera devices. I can't find it now, but I count on help from the community
The crux is to estimate the power on each supply. Worst case approach i.e. a transient current from zero to max may be needed to be on the safe side e.g for a processor that is in deep sleep and goes fully active.
"Poking around until the weirdness disappears?" is of course not a good idea. You don't want to encounter that type of problem...there are enough problems getting a system up and running, so you don't want random glitches making your system go wild. Imagine, you might have verified a system "fully" and everything is fine. Then you add a function, and suddenly it (sometimes) resets in elevated temperature. In that situation, you
really want to be sure that it's NOT the decoupling that is the culprit. And then, if it is, you're still lucky that you found it so early! It could have been a field upgrade that made it crash, and make every customer buy the competitors product next time...