Do you have any references that i can read further on this please?
You're asking the wrong guy for references, unfortunately... I developed this methodology by thinking about the fields. Probably Ott (Henry Ott,
Electromagnetic Compatibility Engineering, Wiley) and such contains this and more?
If others could chime in, that would be great.
I was reviewing another engineer's work the other day and noticed that the analog portion of the board had more than 1 0 ohm link to the main ground plane which contained digital circuitry, without any impedance between them.
Why would this be? I could understand 1 star point and an inductor bead to provide HF impedence but this wasn't there.
Would the multiple connections to ground not cause some sort of ground loop?
A weak ground is almost always a bad idea, and must be used very, very carefully.
It sounds like this was not done in this case...
Appnotes probably suggest it, just because they need to cover a couple of possibilities, even when some of those possibilities are way out in the "you'll never need this" territory. Or, more likely, the authors themselves saw a method and thought "oh hey this looks different, let's put this in", without a care for how devastating it can be to abuse the ground like that.
Multiple points makes ground loop, yes, but how much this matters depends on the voltage between those points. It's usually better to make ground so large and solid that it is solid loops -- this keeps any local current path as short as possible, and as low impedance as possible. Thus, at a distance, the ground loop current, and voltage developed, is very small. Maybe not as small as a carefully tuned split plane, but it requires far, far less experience to pull off correctly.
The grossest mistake made on split planes is routing traces across the split. You put the split there, specifically to
allow a voltage difference between the faces of that gap -- and now you're routing traces clear across it? Not only does this impose 100% of that split voltage upon the traces, it also puts the traces' noise into the gap, making EMC that much worse.
You must route traces across a web connecting the planes. The plane necks down, but does not come to a single point. There cannot be a single point in real electronics (a zero-width trace would be all inductance and resistance, after all). The goal is never "minimize" but "optimize". We cannot get, and do not want, a pointlike plane connection: so what do we want? Well, at least enough width to support the traces crossing the gap. Or, if you've done the split-plane-under-IC thing, then at least the width/length of the IC, and anything that needs to go around it (like supplies). (What ICs usually do internally, is have two connections to the substrate. There is an ohmic connection between DGND and AGND. Imposing voltage across those, causes current to flow through the die itself! Short that out, so the IC isn't getting stressed first of all.)
A necked-down plane is a perfect opportunity to place filters, as well, so that AVCC can be filtered and bypassed to AGND, at the device.
But you see, it quickly gets complicated, and not only is it something no novice or rookie should attempt, but it is something that even a master uses only very rarely.
Tim