Your post is showing the signal being demodulated before even the first pulse has been received, and returning back to '0' immediately after the last pulse has been received. It should be obvious that this will not be possible in practice, unless you have already built a time machine. There will always be some latency between input and output.
If the amplitude and timing of the pulses is well defined as shown i.e. the logic 1 pluses are always significantly higher amplitude than the logic 0 pluses then you may be able to feed the signal into a (very fast) comparator with a suitable threshold set (somewhere between logic o and logic 1 values), and use the output to trigger a (re-triggerable) monostable with a period just slightly longer then the period between your pulses. The downside of this would be noise immunity, and getting the 0/1 duty cycle correct