Designing a self bias N-Ch JFET amplifier (selecting proper Q-values)

[Mozee]

Hello there I've been reading a lot about the J-FET transistors and I was trying to create a JFET amplifier where there is drain resistor and source resistor in the design,  I've read a lot and watched the lot YouTube videos but all seem to be explaining about an already made circuit where Rd and Rs are already chosen!

What I want is to start from scratch. and here are some questions:
1) what are the things that I should know about my design other than Idss and Vgs(off) so basically what are the other constants?
2) what are the thing that I am able to vary using my design for example can I choose my load resistance value even if I pe-set the max drain current of my design e.g. "Id or drain current"?
3) when I try following the graphical mode to find the Q-points I track the transition curve and when I choose the middle point of "Idss which is the max jet current" as Q-point (Id=0.5Idss) in the curve so that maximum swings in "drain current Id" could occur I end up setting Rs because[ Idq=(-1/Rs)*Vgsq where q means the q-point values ] and it's voltage so I cannot add "Rd" resistance any more because doing so will change the total series resistant and "Id" would also change as a result.
what am I doing wrong here? should I consider Vds to have 0.5 Vdd? or Id to be 0.5Idss for a J-FET amplifier for max voltage or current swings?

Note that I want to be able to control the LOAD so I want to be able to set my own load resistance also if possible the Id

[Mozee]

Nothing?

[Cerebus]

I was trying to make a J fat ugly fire

My guess is that people who've seen that have gone "This is an obvious troll" or "Do I really want to spend time working on helping someone who can't even be bothered to get 'JFET amplifier' correct?".

Try again, get your basic terms right, put in some half sane punctuation and aim for sentences that don't have to be read three times to even guess at what you might be asking (and still leave the reader puzzled after guessing). I mean, what in the name of my sainted Aunt does "when I drive following the graphical mode I can drill the transition curve" even mean?

What we have here, if you're not a troll, is English so bad that nobody knows what you mean. On a forum where we've got quite used to coping with broken English from all around the world that's saying something.

Fix that, and I'm sure that someone will jump in to help.

[Zero999]

Nothing?

When you receive no replies, you should think about why. Perhaps no one is interested? Maybe you didn't provide enough information? Or may be your post was so poorly worded and incoherent, no one understood it?

If wording/language isn't your strong point, then how about posting a schematic and some links to the videos you mentioned? That would increase the chance of receiving some helpful replies as we'd have something to look at, rather than a word salad.

[Mozee]

Very sorry about that , was my bad "actually the voice recognition software's bad". I edited the post and attached an image to make the picture clearer for you guys.

Also, Please note that I do know what I am talking about, so no need to explain everything from ground up! just answer my questions and I'll ask If I didn't get your point.

Thanks in advance

[Zero999]

That's better, but I'm still not 100% sure what you're asking.

Yes, you want the voltage across the drain resistor to be half the supply voltage. The source resistor's value will depend on the characteristics of the J-FET, which can vary from device to device, even of the same part number. I wouldn't recommend using a J-FET amplifier to give a large voltage swing, on the output. If a large swing is required, use it as a pre-amplifier do drive another stage, possibly BJT, to get the larger voltage swing.

I can post more on this, but it's getting late, I've not done this for awhile and will need to look it up. I'll add more later. In the mean time, consider re-reading what you've written and I strongly recommend playing with a simulator, such as LTSpice.

[Audioguru]

A Jfet has a wide range of IDSS and cutoff voltage. Do minimum and maximum spec's calculations.

[Keicar]

Yes, the pinchoff voltage V_GS(off) varies along with I_DSS from device-to-device (and they tend to be closely correlated in my experience), so your design will need to be a compromise based on the range of expected values for these parameters.

[Mozee]

That's better, but I'm still not 100% sure what you're asking.

Yes, you want the voltage across the drain resistor to be half the supply voltage. The source resistor's value will depend on the characteristics of the J-FET, which can vary from device to device, even of the same part number.

So the voltage across the drain resistor is to be 1/2VDD and not the voltage across the Drain Source of the Jfet, Now that is new to me and different than the BJT configuration, but are you sure about that, because the output is taken from the drain pin to ground?

more info is really appreciated

[Zero999]

That's better, but I'm still not 100% sure what you're asking.

Yes, you want the voltage across the drain resistor to be half the supply voltage. The source resistor's value will depend on the characteristics of the J-FET, which can vary from device to device, even of the same part number.

So the voltage across the drain resistor is to be 1/2VDD and not the voltage across the Drain Source of the Jfet, Now that is new to me and different than the BJT configuration, but are you sure about that, because the output is taken from the drain pin to ground?

more info is really appreciated

It's no different in that respect to a BJT amplifier. The DC bias voltage across the transistor, is usually less than half the supply voltage, which should be across the collector/drain resistor.

[ferdieCX]

3) when I try following the graphical mode to find the Q-points I track the transition curve and when I choose the middle point of "Idss which is the max jet current" as Q-point (Id=0.5Idss) in the curve so that maximum swings in "drain current Id" could occur I end up setting Rs because[ Idq=(-1/Rs)*Vgsq where q means the q-point values ] and it's voltage so I cannot add "Rd" resistance any more because doing so will change the total series resistant and "Id" would also change as a result.

I suppose, you mean with graphical method that you want to draw the load line over the drain curves.
Just use the Ohm and Kirchoff laws:

Vdd = Vds + Id*(Rs + Rd)
Vgs = Id * Rs

The first one is the static (or DC) load line. It is just a mesh equation

[Mozee]

That's what I meant exactly by the graphical method.

I still find it unclear why would I take the signal out across the drains resistor as the design shows the output taken across drain pin and ground. what am I missing here? and what is the reason to choose this over that one?

[Zero999]

How about trying it in LTSpice? A freely available program, which runs under most Windows versions and under Linux through WINE.

Here's a worked example.

The required output impedance is 10k and supply voltage is 10V, so we want the voltage across the drain resistor to be 5V, therefore the drain and source current will be 0.5mA.

Firstly we look at the drain current vs gate voltage. This can be obtained from the data sheet, but we might as well get LTSpice to plot it. The drain voltage isn't that important and makes very little difference to the current. I chose 5V, because it's half the supply voltage. In final circuit it will be less, since the source resistor will drop some voltage.


The gate voltage, when I_D = 0.5mA is about 2.4V, so that will be the voltage across the source resistor.

RS = V/I = 2.4/0.5*10^-3 = 4800, so use the nearest standard E24 value of 4k7.

The final schematic is shown below, with the DC bias voltages (what you'd measure on a DVM, with no signal applied) labelled. They're slightly different because the resistor value was rounded and the drain current does vary very slightly with differing drain-source voltages.



Alternatively you can just build the circuit with a potentiometer for RS, adjust it for a drain voltage of 5V and then replace it with the appropriate fixed resistor value.

[ferdieCX]

That's what I meant exactly by the graphical method.

I still find it unclear why would I take the signal out across the drains resistor as the design shows the output taken across drain pin and ground. what am I missing here? and what is the reason to choose this over that one?

May be, you have heard about the Superposition theorem.
To analyze a circuit with more than one generator, you analyze it for each generator independently.
The other generators, are replaced by its internal impedance.

In the case of the FET amplifier, the VDD supply has ideally an internal resistance of zero ohms for the AC current.
When you make the signal analysis, VDD looks like a short circuit an the RD is connected between Drain and earth.
You probably think, that your only generator is VDD, so, I have to tell you about device models.
For the AC analysis, the FET behaves like an AC generator, that delivers a current proportional to the input signal vgs.
The following pictures show that. I am sorry, that the text is in Spanish.
Fig. 12 shows the amplifier. Fig 13 is the complete graphical analysis, with both the static and dynamic load lines.
Fig 16 shows the small signal model of the JFET and fig. 17 shows the model of the complete amplifier.

As far as I know, the books in archive.org are in the public domain.
You will find, that this is an excellent book in English:

https://ia801601.us.archive.org/16/items/ElectronicDevicesCircuits/MillmanHalkias-ElectronicDevicesCircuits.pdf

[Zero999]

I still find it unclear why would I take the signal out across the drains resistor as the design shows the output taken across drain pin and ground. what am I missing here? and what is the reason to choose this over that one?

If the circuit were powered from a battery, the signal would look the same, irrespective of whether the oscilloscope's earth clip were connected to the +V rail or 0V rail. As mentioned above, both sides of the power supply are considered to be the same potential, at AC. I'm sure you'll notice that on nearly all power supply circuits, there will be a capacitor connected across the output, which will have a very low impedance to AC signals, hence connecting both rails together, as far as AC is concerned.

[Mozee]

Thank you a lot my friends 

This is exactly what I was missing, or didn't notice probably!
both rails +ve and -ve and considered ground to AC signals so taking the signal across both sides of the FET Drain and Source is actually not different!
Also the LTSpice analysis post has made it so clear for me. Thank you for your time guys, really appreciated.

I will try building a simple JFET amplifier and will see what I will come up with..