Well, how about this: a square wave clock triggers four cascaded monostables. The 500n caps at the emitters generate slow ramps which, when passed to the OR gate, cause delays between pulses. Besides, the 500n stabilize the cascade, which otherwise would respond to both edges of the clock. This is quick and dirty, but uses rather few transistors. There is some trimming to be done with this circuit for it to work to spec, but I guess it should work. By the way, reading rfeecs' reference on PPM signals, for two channels would you need three short pulses?