Now that you've got a visible display things should be a bit easier.
I know most people use a pot from V
SS to V
DD, but your data sheet shows, optimum contrast is obtained between 4.2 and 4.8v (V
DD-V
O) so over 80% of the travel is never used!
The initialisation routine for these displays is not simple, I use the sequence shown in the attachment.
(I tried inserting it as 'code' but the formatting was lost.)
It is important to wait some time after power-up for the display to sort itself out, I use 250mS.
To ensure that the initialisation is bullet proof it is best not to assume the state of the display at the start, hence the repeated lines at the beginning.
The delays are not critical.
One final thought, you are using decoupling capacitors in the supply line aren't you.
(I'd use 100n on the processor, 100n close to the display and a 10u electrolytic somewhere on the board.)
Jim