You are in a breadboard which is a tough environment to start with.
I only see one cap, looks like a tant, on supply rail of breadboard. I would
add another cap close to the pins on the UP or control logic parts. Two
caps, a tant, try 10 uF to start, and a .01 ceramic disk. Each part or adjacent
parts, say every two.
Touching pins and triggering logic sounds like ESD issues. Is the ground on the board
close to source or long lead to source = lots of L = transients.
Pins that interface to outside world should have a low Z interface to minimize C
noise coupling. Thats counter intuitive as it means more Pdiss, the input must source
needed current to meet logic levels/nosie margin, but stray hi z coupling is a issue
especially in CMOS type interfaces. Also pins should have diode protection to clamp
any signal that wants to violate Vdd >= Vin >= Vss.
Regards, Dana.