Erroneous MOSFET drain current measurements.

[bitbanger]

Hi -

This left me scratching my head, so I thought this would be a good place to get some input.

I'm working on the below circuit, a DC load, and attempted to make a measurement of the current entering the drain of the first MOSFET. The total current as metered at my power supply, was 1.0A (correct; 2x setpoint. There are only two channels). Measurement of the first FET yielded only 250mA or so. Thinking something was imbalanced, I measured then the second channel. Same thing, within reason. With ammeter in circuit, I still get 0.050V across both my shunt resistors, so the circuit is operating correctly. However something is influencing the measurement on my 87V.

I checked my 87V at 500mA, 250mA, against a separate supply ammeter, and the fluke agreed just fine. It has always been spot on with my HP 6-1/2 digit, so I have never had reason (or didn't up until now) to believe thet 87V is out of spec.

Both control loops are stable, and each fet is dedicated its own opamp. Any thoughts? I have not yet attempted to measure with my HP bench meter.

PS - circuit credit goes to http://paulorenato.com/joomla/index.php?option=com_content&view=article&id=91:constant-current-load&catid=4:projects&Itemid=4



Best,
James

[bitbanger]

PS - I did also attempt a current measurement of both channels from shunt to ground. While the burden voltage of the ammeter definitely influenced the circuit, the currents agreed with supply/shunt/etc.

[Simon]

So what are the component values, there is not enough information provided.

[kg4arn]

"Both control loops are stable, ..."

Are you sure?  First thing that came to mind was oscillation.

My guess is that you are marginally stable and probing with the DMM leads is pushing the circuit into oscillation.  Probing with different leads/DMM might not always cause the oscillations.

Put a scope on it and then probe around with the DMM leads and see if you can induce the oscillations.  I would also try removing the 30 pF  on the LM324 output pin.

[Andy Watson]

"Both control loops are stable, ..."

Are you sure?  First thing that came to mind was oscillation.

It may be the Fet that is being unstable - that 100nf from the gate to the ground will form a nice high-Q, series L-C circuit.

[mij59]

I don't think the circuit is stable.
Try to measure the ac component with your multimeter.

Remove all capacitors and put a 1nF capacitor between the output of the opamp and the negative input of the opamp.

[T3sl4co1l]

Yeah, putting 100n to ground, right at the gate, is exactly the wrong thing to do...

It should be,
- op-amp output through resistor to gate (100-1000 ohms is fine)
- R+C from op-amp output to -input
- R from shunt resistor to op-amp -input

The series R and across-the-amp R+C set the gain and roll-off of the amp, independent of the transistor capacitance.  Series gate resistor prevents both the op-amp and transistor from oscillating (both are unstable with hard capacitance in those locations).  The fact that the feedback is still correct at DC (the R+C has no effect at DC) means DC current draw is still just as accurate as it should be.

Tim

[bitbanger]

Sorry guys the circuit diagram was wrong - the 30pF should have been from output to inverting input. I've corrected the above drawing.

So I don't know why I didn't see it before, but at *some* current setpoints, the circuit would oscillate wildly (unfortunately the setpoints in question were not one of them). Removed the two 100nF from gate to ground and that took care of things across the entire range (0-2A anyway). Strange because I've been testing for a while and never had any trouble across the range. They were mylar caps, FWIW.

Anyway removing those caps did leave me with a bit more ripple on the output - worst at higher voltages. See below. Also the current measurement inconsistencies are still there - observed opamp outputs when connecting/disconnecting ammeter, and it didn't budge. @50mV across shunt (500mA), 0.211mA into drain. @100mV across shunt (1A), 415mA into drain. 





Cheers,
James

[T3sl4co1l]

Well, that's a little help, but... what is the 30pF going to do against 10 nanos?

What is your ripple coming from?  Is that an output compliance issue (i.e., the output voltage is varying, which is causing the current to not be constant), or something wrong elsewhere in your circuit?

Tim

[bitbanger]

Happy holidays - finally back from a nice, needed hiatus.

Tim, I'm not sure I understand your question, because if I'm being honest I'm not entirely sure of the caps affect on filtering/oscillation in this circuit. Generally I know that any amount of phase difference between output and feedback terminal contributes to oscillation, but this circuit is a little confusing to me because it does not utilize a distinct feedback resistor, as in typical textbook applications (Rin, Rf).

[T3sl4co1l]

What I mean is, if you look at the voltages between op-amp output, -in, and the top of the shunt resistor, you see: 30p, 10n -- a capacitive voltage divider, with rather low gain.  Which means the op-amp won't be seeing much of its own output, and won't have good phase margin.  Eliminating the 10n is equivalent to setting it to ~0p, so the op-amp -in sees 30p from output and the phase margin is good.

Tim

[Circlotron]

The 470R gate resistor should have very short leads and be RIGHT at the (shortened) gate lead of the mosfet. Minimise the inductance of whatever is connected to the gate. The sense resistor in the mosfet source lead if it is wire wound could be inductive. That may not help the situation. Maybe bypass it with a 1uF film cap. It will still resonate with the cap but at a much lower frequency than with the stray capacitance so the phase shift at that lower frequency will hopefully not be enough to allow oscillation.

[T3sl4co1l]

Well, the whole point of using such a large resistance is to prevent inductive and oscillation effects.

Specifically, even for a gate as light as 100pF (which should be well below what Miller effect would allow), you need more than 10uH to begin to see any inductive effects.  That's a lot of wire!

Bypassing the shunt resistor is a bad idea because that will allow larger peak currents (the output will overshoot beyond the required amount) and delay the op-amp's feedback, reducing phase margin.

Source degeneration is generally a very stable connection; the only way to screw it up is to have capacitance directly loading the gate and drain.  But with a hearty resistor on one, it's great.

Tim

[rob77]

one question.. are you feeding the opamp, creating the set voltage  and powering the load with the same supply ? these dummy load circuits like to oscillate in case of weak decoupling.
add some serious decoupling to opamp's power input and if you creating the set voltage with a potenciometer - then make the voltage fed to the potenciometer rock-steady (don't be shy to use several RC filters in series).

but first of all - just as a very quick test - make your set voltage out of a 9V battery + pot, if it stops oscillating then just go ahead with the above

[dannyf]

the circuit would oscillate wildly

You may want to do some ac analysis on the circuit.

On the first glance, I would say that the 470ohm gate resistor is on the high end of a reasonable range. I would try to bring it down to 220 or 110ohm. 22ohm / 47ohm would be on the low-end.

I would get rid of the 30pf capacitor on the gate.

I would reduce the feedback capacitor to maybe 220pf, no more than 1nf. However, I would put a 10nf capacitor from the inverting end to ground, forming a LPF.

[Kevin.D]

It's still oscillating at it's crossover frequency if you look. Remove that 10nF from across the feedback resistor where it's currently doing almost nothing ,and put it where the 30pF currently is.
That will make it stable (at least for most type of  loads).
Regards