Exploiting differences between CMOS and TTL to detect module presence?

[havard]

While reading up on the various logic families, I had an idea. Let's say I'm designing some sort of bus, and the bus controller needs to detect that a module is present but in an uninitialized state.  Adding yet another pin to the bus is out of the question.  There are four bus lines that run directly from a slot to the controller and are not shared with any other device.  Additionally, they will never be held low simultaneously during normal operation.  Let's assume that inputs to the bus controller expect CMOS levels and that all outputs are tri-state and come up in the hi-z state.

Since the minimum VIH of TTL is 2.0V, and CMOS is 3.5V, would it be possible to use a pull up/down arrangement on the module to make the direct-to-controller lines float somewhere above the VIH of TTL but below that of CMOS and then at the controller end use a TTL quad input AND across those lines (say, a 74HCT21) to determine that something is present?  Am I over-complicating the idea?


edit: see attached image for the general idea

[T3sl4co1l]

You could put a weak pull-down on the controller output pins, so that the input bias leakage from a TTL pin generates a detectable threshold.

The threshold must be measured with a comparator, since as you note, the voltage will not reach CMOS levels for the bus circuitry to read directly.  (VIH(min) means, anything between that and VIL(max) (what, 1.5-3.5V?) may be read as high, low or indeterminate (e.g., unstable and oscillating!).)

A potentially deeper question, assuming it matters: how can you tell if the CMOS module is plugged in?  The pins remain hi-Z and no current biases the floating bus pins (a weak pulldown is still recommended, so that a reasonably-well defined voltage still exists -- it'll simply be zero whether anything is connected or not).  A cheap hack could be: a very weak pullup on just one pin, or a set of pins, so that you get a logic vector corresponding to "high Z" = '1' and "really high Z" = '0', which could then be looked up in a table to identify module type or revision or something like that.  Another cheap hack would be sensing power supplied to the module, which again probably needs a resistor in the module, because static CMOS draws basically no current (but the TTL circuit would be detected just fine).

Tim

[havard]

A potentially deeper question, assuming it matters: how can you tell if the CMOS module is plugged in?  The pins remain hi-Z and no current biases the floating bus pins (a weak pulldown is still recommended, so that a reasonably-well defined voltage still exists -- it'll simply be zero whether anything is connected or not).  A cheap hack could be: a very weak pullup on just one pin, or a set of pins, so that you get a logic vector corresponding to "high Z" = '1' and "really high Z" = '0', which could then be looked up in a table to identify module type or revision or something like that.  Another cheap hack would be sensing power supplied to the module, which again probably needs a resistor in the module, because static CMOS draws basically no current (but the TTL circuit would be detected just fine).

See my edit above for the schematic, which hopefully explains what I'm trying to accomplish.

Now that I think about it, this idea really buys me nothing other than a larger BOM and potential headaches.  Seemed like an interesting thought and definitely one I'll play with on the bench, assuming I can stop playing Skyrim for any length of time.  Still, should I ever start the Overly Ambitious Project, I think I'll avoid this specific setup and go for something simpler: start the initialization procedures should the controller see a request from a slot that isn't marked as initialized.

[C]

If you have looked at TTL, you should have noticed that there are three output types
1. totem pole where the ic is actively driving the pin high or low
2. Open colector there the ic can only pull the output low and a resistor pulls the output high
3. Tri-State where the ic adds a Hi-Z state to #1

#2 is a real winner, you can have many outputs all connected to the same signal with out any fighting. Any one or all outputs can pull the signal low. What you have is an active low wired OR gate.  #2 is why you see many buss signals with a bar above the signal name to say the the signal is active low. The problem with #2 is that it is slow compared to #1 & #3.

Again looking at the TTL family you should notice that a lot of the logic has a NOT output. While you may find an AND gate, you will probably find a lot more NAND gates. It is easer to build a NAND gate then an AND gate,

Speed and system noise will cause a lot of problems for your idea. Noise is why you use a schmitt trigger input. With easy access to NAND's and NOR's it is very easy and cheap to have a signal come in to a board or module and go back out in the opposite state. Both of these(NAND NOR) have two inputs so you can easily add a signal from the board or module.

The master puts out a request to the module and the module echo's back and inverted copy of the request. The master knows that the request got to the module and the module is present.
When the module has completed the request, the module uses the second input to the gate to signal it is done. The master seeing returning signal change states again knows the request has been completed. The master can then remove the request signal to the module.
With a resistor pull up at the master, just putting in a module will cause a change back to the master by pulling a line low.

When pushing buss speed the time it takes the Request to go out to the module and then echo back can become a big problem. A very fast module could make the return echo so short that it is hard for the master to detect. 
 
C